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unicorn/qemu/target
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Alistair Francis b44de569f0
target/riscv: Improve the scause logic 
No functional change, just making the code easier to read.

Backports commit 16fdb8ff64374ed51b246437e13043039a8eb9f9 from qemu
2019-05-28 19:14:44 -04:00
..
arm target/arm: Fix vector operation segfault 2019-05-24 18:02:32 -04:00
i386 target/i386: Implement CPUID_EXT_RDRAND 2019-05-23 15:12:50 -04:00
m68k target/m68k: Optimize rotate_x() using extract_i32() 2019-05-17 12:07:07 -04:00
mips tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-16 17:35:37 -04:00
riscv target/riscv: Improve the scause logic 2019-05-28 19:14:44 -04:00
sparc tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-16 17:35:37 -04:00