mirror of
https://github.com/yuzu-emu/unicorn.git
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e1f49dc888
Call the helper_hyp_tlb_flush() function on hfence instructions which will generate an illegal insruction execption if we don't have permission to flush the Hypervisor level TLBs. Backports commit 2761db5fc20943bbd606b6fd49640ac000398de6 from qemu
210 lines
6.2 KiB
C
210 lines
6.2 KiB
C
/*
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* RISC-V Emulation Helpers for QEMU.
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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/* Exceptions processing helpers */
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void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
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uint32_t exception, uintptr_t pc)
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{
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CPUState *cs = env_cpu(env);
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qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception);
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cs->exception_index = exception;
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cpu_loop_exit_restore(cs, pc);
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}
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void helper_raise_exception(CPURISCVState *env, uint32_t exception)
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{
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riscv_raise_exception(env, exception, 0);
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}
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target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
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target_ulong csr)
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{
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target_ulong val = 0;
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if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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return val;
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}
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target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
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target_ulong csr, target_ulong rs1_pass)
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{
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target_ulong val = 0;
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if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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return val;
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}
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target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
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target_ulong csr, target_ulong rs1_pass)
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{
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target_ulong val = 0;
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if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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return val;
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}
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#ifndef CONFIG_USER_ONLY
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target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
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{
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target_ulong prev_priv, prev_virt, mstatus;
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if (!(env->priv >= PRV_S)) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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target_ulong retpc = env->sepc;
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if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
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riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
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}
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if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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mstatus = env->mstatus;
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if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
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/* We support Hypervisor extensions and virtulisation is disabled */
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target_ulong hstatus = env->hstatus;
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prev_priv = get_field(mstatus, MSTATUS_SPP);
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prev_virt = get_field(hstatus, HSTATUS_SPV);
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hstatus = set_field(hstatus, HSTATUS_SPV,
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get_field(hstatus, HSTATUS_SP2V));
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mstatus = set_field(mstatus, MSTATUS_SPP,
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get_field(hstatus, HSTATUS_SP2P));
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hstatus = set_field(hstatus, HSTATUS_SP2V, 0);
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hstatus = set_field(hstatus, HSTATUS_SP2P, 0);
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mstatus = set_field(mstatus, SSTATUS_SIE,
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get_field(mstatus, SSTATUS_SPIE));
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mstatus = set_field(mstatus, SSTATUS_SPIE, 1);
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env->mstatus = mstatus;
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env->hstatus = hstatus;
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if (prev_virt) {
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riscv_cpu_swap_hypervisor_regs(env);
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}
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riscv_cpu_set_virt_enabled(env, prev_virt);
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} else {
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prev_priv = get_field(mstatus, MSTATUS_SPP);
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mstatus = set_field(mstatus, MSTATUS_SIE,
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get_field(mstatus, MSTATUS_SPIE));
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mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
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mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
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env->mstatus = mstatus;
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}
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riscv_cpu_set_mode(env, prev_priv);
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return retpc;
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}
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target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
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{
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if (!(env->priv >= PRV_M)) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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target_ulong retpc = env->mepc;
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if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
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riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
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}
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target_ulong mstatus = env->mstatus;
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target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
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target_ulong prev_virt = MSTATUS_MPV_ISSET(env);
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mstatus = set_field(mstatus, MSTATUS_MIE,
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get_field(mstatus, MSTATUS_MPIE));
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mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
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mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
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#ifdef TARGET_RISCV32
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env->mstatush = set_field(env->mstatush, MSTATUS_MPV, 0);
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#else
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mstatus = set_field(mstatus, MSTATUS_MPV, 0);
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#endif
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env->mstatus = mstatus;
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riscv_cpu_set_mode(env, prev_priv);
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if (riscv_has_ext(env, RVH)) {
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if (prev_virt) {
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riscv_cpu_swap_hypervisor_regs(env);
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}
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riscv_cpu_set_virt_enabled(env, prev_virt);
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}
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return retpc;
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}
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void helper_wfi(CPURISCVState *env)
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{
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CPUState *cs = env_cpu(env);
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if ((env->priv == PRV_S &&
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get_field(env->mstatus, MSTATUS_TW)) ||
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riscv_cpu_virt_enabled(env)) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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} else {
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cs->halted = 1;
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cs->exception_index = EXCP_HLT;
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cpu_loop_exit(cs);
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}
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}
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void helper_tlb_flush(CPURISCVState *env)
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{
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CPUState *cs = env_cpu(env);
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if (!(env->priv >= PRV_S) ||
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(env->priv == PRV_S &&
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get_field(env->mstatus, MSTATUS_TVM))) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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} else {
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tlb_flush(cs);
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}
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}
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void helper_hyp_tlb_flush(CPURISCVState *env)
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{
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CPUState *cs = env_cpu(env);
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if (env->priv == PRV_M ||
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(env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) {
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tlb_flush(cs);
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return;
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}
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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#endif /* !CONFIG_USER_ONLY */
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