11 commits

Author	SHA1	Message	Date
Alistair Francis	e1f49dc888	target/riscv: Implement checks for hfence ... Call the helper_hyp_tlb_flush() function on hfence instructions which will generate an illegal insruction execption if we don't have permission to flush the Hypervisor level TLBs. Backports commit 2761db5fc20943bbd606b6fd49640ac000398de6 from qemu	2021-02-25 12:03:57 -05:00
Alistair Francis	2584ab8ee5	target/riscv: Drop support for ISA spec version 1.09.1 ... The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since 4.1. It's not commonly used so let's remove support for it. Backports commit 1a9540d1f1a9c5022d9273d0244e5809679dd33b from qemu	2020-06-14 22:23:26 -04:00
Alistair Francis	1001f0ba1f	target/riscv: Correctly implement TSR trap ... As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't correctly handling illegal instructions based on the value of MSTATUS_TSR and the current privledge level. This patch fixes the issue raised in the bug by raising an illegal instruction if TSR is set and we are in S-Mode. Backports commit ed5abf46b3c414ef58e647145f19b3966700b206 from qemu	2020-04-30 06:19:49 -04:00
Alistair Francis	6c3338430a	target/riscv: Add the MSTATUS_MPV_ISSET helper macro ... Add a helper macro MSTATUS_MPV_ISSET() which will determine if the MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V. Backports commit e44b50b5b2e508fdd24915ab0e44ac49685e1de3 from qemu	2020-03-22 02:18:02 -04:00
Alistair Francis	835b025692	target/riscv: Add support for the 32-bit MSTATUSH CSR ... Backports commit 551fa7e8a695ea5fd1cca8ffd318556855bbf54f from qemu	2020-03-22 02:16:13 -04:00
Alistair Francis	fcc30eac4d	target/riscv: Add Hypervisor trap return support ... Backports commit e3fba4bab668a41f7cec6405c5aeb21497bd7c83 from qemu	2020-03-22 01:41:58 -04:00
Alistair Francis	f6b14e146e	target/riscv: Generate illegal instruction on WFI when V=1 ... Backports commit 9d0d11269671646be7475cc01142e9d3ed8ae59c from qemu	2020-03-22 01:38:14 -04:00
Yiting Wang	1c7f2083da	riscv: Set xPIE to 1 after xRET ... When executing an xRET instruction, supposing xPP holds the value y, xIE is set to xPIE; the privilege mode is changed to y; xPIE is set to 1. But QEMU sets xPIE to 0 incorrectly. Backports commit a37f21c27d3e2342c2080aafd4cfe7e949612428 from qemu	2020-03-21 12:18:59 -04:00
Richard Henderson	47b797f1bb	target/riscv: Use env_cpu, env_archcpu ... Cleanup in the boilerplate that each target must define. Replace riscv_env_get_cpu with env_archcpu. The combination CPU(riscv_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Backports commit 3109cd98a6c0c618189b38a83a8aa29cb20acbce from qemu	2019-06-12 12:06:19 -04:00
Jonathan Behrens	25c0333213	target/riscv: Do not allow sfence.vma from user mode ... The 'sfence.vma' instruction is privileged, and should only ever be allowed when executing in supervisor mode or higher. Backports commit b86f4167630802128d94f3c89043d97d2f4c2546 from qemu	2019-05-28 18:29:46 -04:00
Lioncash	b6f752970b	target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.	2019-03-08 21:46:10 -05:00