Bastian Koppelmann b9eda7c464 target/riscv: Remove shift and slt insn manual decoding ... Backports commit 34446e845829f55eaa9a07a915950af0b2710b47 from qemu		2019-03-19 05:23:47 -04:00
..
arm	Add ARM MSP, PSP and CONTROL register access (#1071)	2019-03-08 02:24:49 -05:00
i386	i386: extended the cpuid_level when Intel PT is enabled	2019-03-11 16:40:23 -04:00
m68k	target/m68k: Correct instruction emulation	2019-02-28 19:21:49 -05:00
mips	target/mips: Restore Qemu's organization of CPU definitions	2019-03-08 01:40:50 -05:00
riscv	target/riscv: Remove shift and slt insn manual decoding	2019-03-19 05:23:47 -04:00
sparc	target: Resolve repeated typedef warnings	2019-01-22 20:27:35 -05:00