Emilio G. Cota c1e26c4e35 tcg: check CF_PARALLEL instead of parallel_cpus ... Thereby decoupling the resulting translated code from the current state of the system. The tb->cflags field is not passed to tcg generation functions. So we add a field to TCGContext, storing there a copy of tb->cflags. Most architectures have <= 32 registers, which results in a 4-byte hole in TCGContext. Use this hole for the new field. Backports commit e82d5a2460b0e176128027651ff9b104e4bdf5cc from qemu		2019-05-06 00:52:08 -04:00
..
atomic_template.h	tcg: Fix LGPL version number	2019-02-03 17:55:28 -05:00
cpu-exec-common.c	tcg: Fix LGPL version number	2019-02-03 17:55:28 -05:00
cpu-exec.c	tcg: Add CPUState cflags_next_tb	2019-05-04 22:30:22 -04:00
cputlb.c	cputlb: Fix io_readx() to respect the access_type	2019-04-30 10:11:11 -04:00
Makefile.objs	tcg: move tcg backend files into accel/tcg/	2018-03-13 11:48:15 -04:00
softmmu_template.h	cputlb: Synchronize with qemu	2019-04-26 15:48:45 -04:00
tcg-runtime-gvec.c	tcg: Fix LGPL version number	2019-02-03 17:55:28 -05:00
tcg-runtime.c	tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK	2019-05-04 22:22:06 -04:00
tcg-runtime.h	tcg: Synchronize with qemu	2019-04-26 09:32:20 -04:00
translate-all.c	tcg: check CF_PARALLEL instead of parallel_cpus	2019-05-06 00:52:08 -04:00
translate-all.h	tcg: Synchronize with qemu	2019-04-26 09:32:20 -04:00
translate-common.c	tcg: Fix LGPL version number	2019-02-03 17:55:28 -05:00
translator.c	tcg: Hoist max_insns computation to tb_gen_code	2019-04-30 09:49:57 -04:00