Richard Henderson d1ad8bf44c target/riscv: Add checks for several RVC reserved operands ... C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved operands that were not diagnosed. Backports commit 4cc16b3b9282e04fab8e84d136540757e82af019 from qemu		2019-05-28 19:20:36 -04:00
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arm	target/arm: Fix vector operation segfault	2019-05-24 18:02:32 -04:00
i386	target/i386: Implement CPUID_EXT_RDRAND	2019-05-23 15:12:50 -04:00
m68k	target/m68k: Optimize rotate_x() using extract_i32()	2019-05-17 12:07:07 -04:00
mips	tcg: Use CPUClass::tlb_fill in cputlb.c	2019-05-16 17:35:37 -04:00
riscv	target/riscv: Add checks for several RVC reserved operands	2019-05-28 19:20:36 -04:00
sparc	tcg: Use CPUClass::tlb_fill in cputlb.c	2019-05-16 17:35:37 -04:00