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unicorn/qemu/target/riscv/insn_trans
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Tony Nguyen f75368cd0f
tcg: TCGMemOp is now accelerator independent MemOp 
Preparation for collapsing the two byte swaps, adjust_endianness and
handle_bswap, along the I/O path.

Target dependant attributes are conditionalized upon NEED_CPU_H.

Backports commit 14776ab5a12972ea439c7fb2203a4c15a09094b4 from qemu
2019-11-28 03:01:12 -05:00
..
trans_privileged.inc.c target/riscv: Add the privledge spec version 1.11.0 2019-08-08 17:03:33 -04:00
trans_rva.inc.c tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
trans_rvd.inc.c target/riscv: Convert RV64D insns to decodetree 2019-03-18 16:57:16 -04:00
trans_rvf.inc.c target/riscv: Convert RV64F insns to decodetree 2019-03-18 16:43:17 -04:00
trans_rvi.inc.c tcg: TCGMemOp is now accelerator independent MemOp 2019-11-28 03:01:12 -05:00
trans_rvm.inc.c target/riscv: Zero extend the inputs of divuw and remuw 2019-03-26 20:38:17 -04:00