Michael Clark d3dbcb6dfc RISC-V: Add support for vectored interrupts ... If vectored interrupts are enabled (bits[1:0] of mtvec/stvec == 1) then use the following logic for trap entry address calculation: pc = mtvec + cause * 4 In addition to adding support for vectored interrupts this patch simplifies the interrupt delivery logic by making sync/async cause decoding and encoding steps distinct. The cause code and the sign bit indicating sync/async is split at the beginning of the function and fixed cause is renamed to cause. The MSB setting for async traps is delayed until setting mcause/scause to allow redundant variables to be eliminated. Some variables are renamed for conciseness and moved so that decls are at the start of the block. Backports commit acbbb94e5730c9808830938e869d243014e2923a from qemu		2019-03-19 23:58:31 -04:00
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arm	target/arm: Check access permission to ADDVL/ADDPL/RDVL	2019-03-19 05:42:59 -04:00
i386	i386: extended the cpuid_level when Intel PT is enabled	2019-03-11 16:40:23 -04:00
m68k	target/m68k: Correct instruction emulation	2019-02-28 19:21:49 -05:00
mips	target/mips: Restore Qemu's organization of CPU definitions	2019-03-08 01:40:50 -05:00
riscv	RISC-V: Add support for vectored interrupts	2019-03-19 23:58:31 -04:00
sparc	target: Resolve repeated typedef warnings	2019-01-22 20:27:35 -05:00