Michael Clark d3dbcb6dfc RISC-V: Add support for vectored interrupts ... If vectored interrupts are enabled (bits[1:0] of mtvec/stvec == 1) then use the following logic for trap entry address calculation: pc = mtvec + cause * 4 In addition to adding support for vectored interrupts this patch simplifies the interrupt delivery logic by making sync/async cause decoding and encoding steps distinct. The cause code and the sign bit indicating sync/async is split at the beginning of the function and fixed cause is renamed to cause. The MSB setting for async traps is delayed until setting mcause/scause to allow redundant variables to be eliminated. Some variables are renamed for conciseness and moved so that decls are at the start of the block. Backports commit acbbb94e5730c9808830938e869d243014e2923a from qemu		2019-03-19 23:58:31 -04:00
..
accel	cputlb: update TLB entry/index after tlb_fill	2019-02-12 11:48:48 -05:00
crypto
default-configs	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
docs	docs/devel/memory.txt: Document _with_attrs accessors	2018-10-04 04:46:26 -04:00
fpu	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
hw	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
include	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
qapi	qapi: Rewrite string-input-visitor's integer and list parsing	2018-12-18 04:57:25 -05:00
qobject	qstring: Move qstring_from_substr()'s @end one to the right	2018-08-02 21:24:19 -04:00
qom	qom/cpu: Add cluster_index to CPUState	2019-01-30 12:59:59 -05:00
scripts	decodetree: Properly diagnose fields overflowing an insn	2019-03-13 11:21:04 -04:00
target	RISC-V: Add support for vectored interrupts	2019-03-19 23:58:31 -04:00
tcg	target/riscv: Initial introduction of the RISC-V target	2019-03-08 21:46:10 -05:00
util	mmap-alloc: fix hugetlbfs misaligned length in ppc64	2019-02-05 16:52:39 -05:00
aarch64.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
aarch64eb.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
accel.c
arm.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
armeb.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
CODING_STYLE
configure	configure: Disable W^X on OpenBSD	2019-03-11 16:46:52 -04:00
COPYING
COPYING.LIB
cpus.c
exec.c	exec.c: refactor function flatview_add_to_dispatch()	2019-03-11 17:00:46 -04:00
gen_all_header.sh
glib_compat.c	target/arm: expose remaining CPUID registers as RAZ	2019-02-15 17:48:37 -05:00
HACKING
header_gen.py	RISC-V: Allow interrupt controllers to claim interrupts	2019-03-19 23:48:12 -04:00
ioport.c
LICENSE
m68k.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
Makefile	Revert "Makefile: Rename TARGET_DIRS to TARGET_LIST"	2018-07-05 17:40:24 -04:00
Makefile.objs
Makefile.target	configure: Remove old -fno-gcse workaround for GCC 4.6.x and 4.7.[012]	2018-12-18 03:52:36 -05:00
memory.c	memory: learn about non-volatile memory region	2018-11-11 08:50:39 -05:00
memory_ldst.inc.c	exec: Fix MAP_RAM for cached access	2018-07-03 01:11:12 -04:00
memory_mapping.c
mips.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
mips64.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
mips64el.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
mipsel.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
powerpc.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
qemu-timer.c
riscv32.h	RISC-V: Allow interrupt controllers to claim interrupts	2019-03-19 23:48:12 -04:00
riscv64.h	RISC-V: Allow interrupt controllers to claim interrupts	2019-03-19 23:48:12 -04:00
rules.mak
sparc.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
sparc64.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00
unicorn_common.h	unicorn_common: Fix unicorn memory functions failing	2018-09-03 10:40:14 -04:00
VERSION	Open 4.0 development tree	2018-12-11 20:33:45 -05:00
vl.c
vl.h
x86_64.h	qemu/fpu: Synchronize with Qemu	2019-03-09 18:27:31 -05:00