Mateja Marjanovic d50a1fef6b target/mips: Preparing for adding MMI instructions ... Set up MMI code to be compiled only for TARGET_MIPS64. This is needed so that GPRs are 64 bit, and combined with MMI registers, they will form full 128 bit registers. Backports commit 37b9aae2e6e005e6df206a0b4804972460806166 from qemu		2019-02-28 16:15:47 -05:00
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arm	target/arm: Enable ARMv8.2-FHM for -cpu max	2019-02-28 15:47:03 -05:00
i386	Revert "i386: Add CPUID bit for PCONFIG"	2019-02-07 08:56:40 -05:00
m68k	target/m68k: Fix LGPL information in the file headers	2019-02-03 17:55:29 -05:00
mips	target/mips: Preparing for adding MMI instructions	2019-02-28 16:15:47 -05:00
sparc	target: Resolve repeated typedef warnings	2019-01-22 20:27:35 -05:00