Yongbok Kim d65583df80 target-mips: add CMGCRBase register ... Physical base address for the memory-mapped Coherency Manager Global Configuration Register space. The MIPS default location for the GCR_BASE address is 0x1FBF_8. This register only exists if Config3 CMGCR is set to one. Backports commit c870e3f52cac0c8a4a1377398327c4ff20d49d41 from qemu		2018-02-22 10:43:26 -05:00
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cpu-qom.h	remove slow cpu QOM casts (#815)	2017-05-02 14:56:39 +08:00
cpu.c	include/qemu/osdep.h: Don't include qapi/error.h	2018-02-21 23:08:18 -05:00
cpu.h	target-mips: add CMGCRBase register	2018-02-22 10:43:26 -05:00
dsp_helper.c	mips: Clean up includes	2018-02-19 00:45:08 -05:00
helper.c	mips: Clean up includes	2018-02-19 00:45:08 -05:00
helper.h	target-mips: implement R6 multi-threading	2018-02-20 22:02:40 -05:00
lmi_helper.c	mips: Clean up includes	2018-02-19 00:45:08 -05:00
Makefile.objs	import	2015-08-21 15:04:50 +08:00
mips-defs.h	target-mips: fix MIPS64R6-generic configuration	2018-02-17 15:23:21 -05:00
msa_helper.c	mips: Clean up includes	2018-02-19 00:45:08 -05:00
op_helper.c	target-mips: implement R6 multi-threading	2018-02-20 22:02:40 -05:00
TODO	import	2015-08-21 15:04:50 +08:00
translate.c	target-mips: add CMGCRBase register	2018-02-22 10:43:26 -05:00
translate_init.c	target-mips: implement R6 multi-threading	2018-02-20 22:02:40 -05:00
unicorn.c	tcg: Make cpu_gpr a TCGv array	2018-02-21 01:02:46 -05:00
unicorn.h	armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition.	2017-03-15 22:25:35 +08:00