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Richard Henderson dc087c4c0c
target/riscv: Merge argument sets for insn32 and insn16 
In some cases this allows us to directly use the insn32
translator function. In some cases we still need a shim.

Backports commit e1d455dd91c935c714412dafeb24db947429a929 from qemu
2019-05-28 18:50:48 -04:00
..
arm target/arm: Fix vector operation segfault 2019-05-24 18:02:32 -04:00
i386 target/i386: Implement CPUID_EXT_RDRAND 2019-05-23 15:12:50 -04:00
m68k target/m68k: Optimize rotate_x() using extract_i32() 2019-05-17 12:07:07 -04:00
mips tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-16 17:35:37 -04:00
riscv target/riscv: Merge argument sets for insn32 and insn16 2019-05-28 18:50:48 -04:00
sparc tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-16 17:35:37 -04:00