Richard Henderson dc087c4c0c target/riscv: Merge argument sets for insn32 and insn16 ... In some cases this allows us to directly use the insn32 translator function. In some cases we still need a shim. Backports commit e1d455dd91c935c714412dafeb24db947429a929 from qemu		2019-05-28 18:50:48 -04:00
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trans_privileged.inc.c	RISC-V: fix single stepping over ret and other branching instructions	2019-05-28 18:35:07 -04:00
trans_rva.inc.c	target/riscv: Convert RV64A insns to decodetree	2019-03-18 16:27:53 -04:00
trans_rvc.inc.c	target/riscv: Merge argument sets for insn32 and insn16	2019-05-28 18:50:48 -04:00
trans_rvd.inc.c	target/riscv: Convert RV64D insns to decodetree	2019-03-18 16:57:16 -04:00
trans_rvf.inc.c	target/riscv: Convert RV64F insns to decodetree	2019-03-18 16:43:17 -04:00
trans_rvi.inc.c	RISC-V: fix single stepping over ret and other branching instructions	2019-05-28 18:35:07 -04:00
trans_rvm.inc.c	target/riscv: Zero extend the inputs of divuw and remuw	2019-03-26 20:38:17 -04:00