Peter Maydell dc44eded51 arm: Don't decode MRS(banked) or MSR(banked) for M profile ... M profile doesn't have the MSR(banked) and MRS(banked) instructions and uses the encodings for different kinds of M-profile MRS/MSR. Guard the relevant bits of the decode logic to make sure we don't accidentally fall into them by accident on M-profile. (The bit being checked for this (bit 5) is part of the SYSm field on M-profile, but since no currently allocated system registers have encodings with bit 5 of SYSm set, this hasn't been a problem in practice.) Backports commit 43ac65742319ef5ac4461daf43316b189cd21e89 from qemu		2018-03-02 13:08:20 -05:00
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arm	arm: Don't decode MRS(banked) or MSR(banked) for M profile	2018-03-02 13:08:20 -05:00
i386	i386: Change stepping of Haswell to non-blacklisted value	2018-03-02 12:53:11 -05:00
m68k	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
mips	target-mips: Provide function to test if a CPU supports an ISA	2018-03-02 08:20:19 -05:00
sparc	cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap	2018-03-02 10:12:40 -05:00