unicorn/qemu/include
David Hildenbrand de513617c8 accel/tcg: allow to invalidate a write TLB entry immediately
Background: s390x implements Low-Address Protection (LAP). If LAP is
enabled, writing to effective addresses (before any translation)
0-511 and 4096-4607 triggers a protection exception.

So we have subpage protection on the first two pages of every address
space (where the lowcore - the CPU private data resides).

By immediately invalidating the write entry but allowing the caller to
continue, we force every write access onto these first two pages into
the slow path. we will get a tlb fault with the specific accessed
addresses and can then evaluate if protection applies or not.

We have to make sure to ignore the invalid bit if tlb_fill() succeeds.

Backports commit f52bfb12143e29d7c8bd827bdb751aee47a9694e from qemu
2020-01-14 07:14:10 -05:00
..
crypto Drop unused crypto source files 2018-02-17 15:23:57 -05:00
exec accel/tcg: allow to invalidate a write TLB entry immediately 2020-01-14 07:14:10 -05:00
fpu fpu: make softfloat-macros self-contained 2019-11-18 21:10:39 -05:00
hw target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
qapi qapi: Rewrite string-input-visitor's integer and list parsing 2018-12-18 04:57:25 -05:00
qemu typedefs: Separate incomplete types and function types 2019-11-18 16:42:51 -05:00
qom cputlb: Handle watchpoints via TLB_WATCHPOINT 2020-01-14 06:58:33 -05:00
sysemu accel: Remove unused AccelClass::available field 2019-05-03 11:31:27 -04:00
config.h import 2015-08-21 15:04:50 +08:00
elf.h include/elf: Update elf.h to commit f71a8eaffba3271cf7cdad95572f6996f7523a5b 2018-03-11 15:34:35 -04:00
glib_compat.h target/arm/translate: Synchronize with Qemu 2019-04-27 10:13:01 -04:00
qemu-common.h tcg: Add EXCP_ATOMIC 2018-02-27 11:57:58 -05:00