Georg Kotheimer e74588a57f target/riscv: Use background registers also for MSTATUS_MPV ... The current condition for the use of background registers only considers the hypervisor load and store instructions, but not accesses from M mode via MSTATUS_MPRV+MPV. Backports db9ab38b81058b41e5f469165067feea46762eee		2021-03-30 15:14:13 -04:00
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arm	target/arm: Update sve reduction vs simd_desc	2021-03-30 14:44:53 -04:00
i386	qemu/atomic.h: rename atomic_ to qatomic_	2021-03-08 14:34:35 -05:00
m68k	target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature	2021-03-12 14:55:43 -05:00
mips	mips: Fix build	2021-03-05 08:51:51 -05:00
riscv	target/riscv: Use background registers also for MSTATUS_MPV	2021-03-30 15:14:13 -04:00
sparc	sparc: Fix build	2021-03-05 08:54:43 -05:00