Alistair Francis ea2fee2d4d target/riscv: Add a base 32 and 64 bit CPU ... At the same time deprecate the ISA string CPUs. It is dobtful anyone specifies the CPUs, but we are keeping them for the Spike machine (which is about to be depreated) so we may as well just mark them as deprecated. Backports commit 8903bf6e6d73d03b988b4a8197132de2ad681ff5 from qemu		2019-05-28 19:11:12 -04:00
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arm	target/arm: Fix vector operation segfault	2019-05-24 18:02:32 -04:00
i386	target/i386: Implement CPUID_EXT_RDRAND	2019-05-23 15:12:50 -04:00
m68k	target/m68k: Optimize rotate_x() using extract_i32()	2019-05-17 12:07:07 -04:00
mips	tcg: Use CPUClass::tlb_fill in cputlb.c	2019-05-16 17:35:37 -04:00
riscv	target/riscv: Add a base 32 and 64 bit CPU	2019-05-28 19:11:12 -04:00
sparc	tcg: Use CPUClass::tlb_fill in cputlb.c	2019-05-16 17:35:37 -04:00