Peter Maydell ebe442b1d4 target/arm: Implement HCR.PTW ... If the HCR_EL2 PTW virtualizaiton configuration register bit is set, then this means that a stage 2 Permission fault must be generated if a stage 1 translation table access is made to an address that is mapped as Device memory in stage 2. Implement this. Backports commit eadb2febf05452bd8062c4c7823d7d789142500c from qemu		2018-11-10 09:25:57 -05:00
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arm	target/arm: Implement HCR.PTW	2018-11-10 09:25:57 -05:00
i386	target/i386: Convert to HAVE_CMPXCHG128	2018-10-23 15:21:03 -04:00
m68k	Removes accessible assert	2018-10-06 05:02:20 -04:00
mips	target/mips: Add opcodes for nanoMIPS EVA instructions	2018-10-23 14:33:08 -04:00
sparc	Sparc increase ttl number	2018-10-06 04:55:52 -04:00