Aleksandar Markovic ed037799c7 target/mips: Amend MXU instruction opcodes ... Amend MXU instruction opcodes. Pool04 is actually only instruction OPC_MXU_S16MAD. Two cases within S16MAD are recognized by 1-bit subfield 'aptn1'. Backports commit eab0bdb07cbed1131be2d1f541059c7b96b05e32 from qemu		2018-11-11 05:58:35 -05:00
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arm	target/arm: Only flush tlb if ASID changes	2018-11-10 11:26:24 -05:00
i386	target/i386: Convert to HAVE_CMPXCHG128	2018-10-23 15:21:03 -04:00
m68k	Removes accessible assert	2018-10-06 05:02:20 -04:00
mips	target/mips: Amend MXU instruction opcodes	2018-11-11 05:58:35 -05:00
sparc	Sparc increase ttl number	2018-10-06 04:55:52 -04:00