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Amend MXU instruction opcodes. Pool04 is actually only instruction OPC_MXU_S16MAD. Two cases within S16MAD are recognized by 1-bit subfield 'aptn1'. Backports commit eab0bdb07cbed1131be2d1f541059c7b96b05e32 from qemu |
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arm | ||
i386 | ||
m68k | ||
mips | ||
sparc |