Richard Henderson ede1cae3dc tcg: Lower indirect registers in a separate pass ... Rather than rely on recursion during the middle of register allocation, lower indirect registers to loads and stores off the indirect base into plain temps. For an x86_64 host, with sufficient registers, this results in identical code, modulo the actual register assignments. For an i686 host, with insufficient registers, this means that temps can be (temporarily) spilled to the stack in order to satisfy an allocation. This as opposed to the possibility of not being able to spill, to allocate a register for the indirect base, in order to perform a spill. Backports commit 5a18407f55ade924aa6397c9a043a9ffd59645fe from qemu		2018-02-25 22:32:28 -05:00
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crypto	Drop unused crypto source files	2018-02-17 15:23:57 -05:00
exec	tcg: Reorg TCGOp chaining	2018-02-25 21:44:50 -05:00
fpu	Clean up decorations and whitespace around header guards	2018-02-25 04:26:02 -05:00
hw	target-i386: Add x86_cpu_unrealizefn()	2018-02-25 20:54:13 -05:00
qapi	Clean up header guards that don't match their file name	2018-02-25 04:18:42 -05:00
qemu	tcg: Lower indirect registers in a separate pass	2018-02-25 22:32:28 -05:00
qom	Fix confusing argument names in some common functions	2018-02-25 03:58:27 -05:00
sysemu	accel: make configure_accelerator return void	2018-02-24 00:31:28 -05:00
config.h	import	2015-08-21 15:04:50 +08:00
elf.h	fix merge conflicts	2017-03-10 21:04:33 +08:00
glib_compat.h	qapi: Fix memleak in string visitors on int lists	2018-02-25 00:20:34 -05:00
qemu-common.h	qemu-common.h: Drop WORDS_ALIGNED define	2018-02-24 17:01:55 -05:00