Soren Brinkmann fd2ac3058f target-arm: A64: Print ELR when taking exceptions ... When taking an exception print the content of the exception link register. This is useful especially for synchronous exceptions because in that case this registers holds the address of the instruction that generated the exception. Backports commit b21ab1fc217b4a2b8f2f85d16bdd8510a7817a34 from qemu		2018-02-17 15:23:13 -05:00
..
default-configs
docs
fpu
hw	qerror: Clean up QERR_ macros to expand into a single string	2018-02-17 15:23:09 -05:00
include	qerror: Move #include out of qerror.h	2018-02-17 15:23:10 -05:00
qapi	qerror: Clean up QERR_ macros to expand into a single string	2018-02-17 15:23:09 -05:00
qobject	qerror: Finally unused, clean up	2018-02-17 15:23:10 -05:00
qom	qerror: Clean up QERR_ macros to expand into a single string	2018-02-17 15:23:09 -05:00
scripts
target-arm	target-arm: A64: Print ELR when taking exceptions	2018-02-17 15:23:13 -05:00
target-i386	qerror: Clean up QERR_ macros to expand into a single string	2018-02-17 15:23:09 -05:00
target-m68k	m68k: fix usp processing on interrupt entry and exception exit	2018-02-17 15:23:09 -05:00
target-mips	target-mips: add mips32r6-generic CPU definition	2018-02-17 15:23:13 -05:00
target-sparc
tcg	tcg: add TCG_TARGET_TLB_DISPLACEMENT_BITS	2018-02-13 08:28:29 -05:00
util	bitmap: add atomic test and clear	2018-02-13 10:02:12 -05:00
aarch64.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
aarch64eb.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
accel.c	Automated leading tab to spaces conversion.	2017-01-21 12:28:22 +11:00
arm.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
armeb.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
CODING_STYLE
configure
COPYING
COPYING.LIB
cpu-exec.c
cpus.c
cputlb.c	memory: replace cpu_physical_memory_reset_dirty() with test-and-clear	2018-02-13 11:25:45 -05:00
exec.c	memory: replace cpu_physical_memory_reset_dirty() with test-and-clear	2018-02-13 11:25:45 -05:00
gen_all_header.sh
glib_compat.c
HACKING
header_gen.py	target-mips: add ERETNC instruction and Config5.LLB bit	2018-02-13 13:33:37 -05:00
ioport.c
LICENSE	import	2015-08-21 15:04:50 +08:00
m68k.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
Makefile
Makefile.objs
Makefile.target
memory.c	memory: use mr->ram_addr in "is this RAM?" assertions	2018-02-13 11:31:02 -05:00
memory_mapping.c
mips.h	target-mips: add ERETNC instruction and Config5.LLB bit	2018-02-13 13:33:37 -05:00
mips64.h	target-mips: add ERETNC instruction and Config5.LLB bit	2018-02-13 13:33:37 -05:00
mips64el.h	target-mips: add ERETNC instruction and Config5.LLB bit	2018-02-13 13:33:37 -05:00
mipsel.h	target-mips: add ERETNC instruction and Config5.LLB bit	2018-02-13 13:33:37 -05:00
powerpc.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
qapi-schema.json
qemu-log.c
qemu-timer.c
rules.mak
softmmu_template.h	Add MemTxAttrs to the IOTLB	2018-02-12 18:38:38 -05:00
sparc.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
sparc64.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00
tcg-runtime.c
translate-all.c	translate-all: fix watchpoints if retranslation not possible	2018-02-17 15:22:43 -05:00
translate-all.h	translate-all: remove unnecessary argument to tb_invalidate_phys_range	2018-02-13 09:04:51 -05:00
unicorn_common.h
VERSION
vl.c
vl.h
x86_64.h	target-mips: Misaligned memory accesses for MSA	2018-02-13 13:27:31 -05:00