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unicorn/qemu/target/riscv/insn16.decode

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target/riscv: Convert quadrant 0 of RVXC insns to decodetree
2019-03-19 08:45:40 +00:00
#
# RISC-V translation routines for the RVXI Base Integer Instruction Set.
#
# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
#
# This program is free software; you can redistribute it and/or modify it
# under the terms and conditions of the GNU General Public License,
# version 2 or later, as published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
#
# You should have received a copy of the GNU General Public License along with
# this program. If not, see <http://www.gnu.org/licenses/>.
# Fields:
%rd 7:5
%rs1_3 7:3 !function=ex_rvc_register
%rs2_3 2:3 !function=ex_rvc_register
target/riscv: Convert quadrant 2 of RVXC insns to decodetree Backports commit 97b0be81f6f20bfd53725cb2500b47c6786be532 from qemu
2019-03-19 08:53:05 +00:00
%rs2_5 2:5
target/riscv: Convert quadrant 0 of RVXC insns to decodetree
2019-03-19 08:45:40 +00:00
# Immediates:
target/riscv: Convert quadrant 1 of RVXC insns to decodetree Backports commit 07b001c6fc500fa0e87fd8210f270d7dc8aff9ea from qemu
2019-03-19 08:50:05 +00:00
%imm_ci 12:s1 2:5
target/riscv: Convert quadrant 0 of RVXC insns to decodetree
2019-03-19 08:45:40 +00:00
%nzuimm_ciw 7:4 11:2 5:1 6:1 !function=ex_shift_2
%uimm_cl_d 5:2 10:3 !function=ex_shift_3
%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2
target/riscv: Convert quadrant 1 of RVXC insns to decodetree Backports commit 07b001c6fc500fa0e87fd8210f270d7dc8aff9ea from qemu
2019-03-19 08:50:05 +00:00
%imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
target/riscv: Merge argument decode for RVC shifti Special handling for IMM==0 is the only difference between RVC shifti and RVI shifti. This can be handled with !function. Backports commit 6cafec92f1c862a9754ef6a28be68ba7178a284d from qemu
2019-05-28 22:52:47 +00:00
%shimm_6bit 12:1 2:5 !function=ex_rvc_shifti
target/riscv: Convert quadrant 2 of RVXC insns to decodetree Backports commit 97b0be81f6f20bfd53725cb2500b47c6786be532 from qemu
2019-03-19 08:53:05 +00:00
%uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3
%uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2
%uimm_6bit_sd 7:3 10:3 !function=ex_shift_3
%uimm_6bit_sw 7:2 9:4 !function=ex_shift_2
target/riscv: Convert quadrant 1 of RVXC insns to decodetree Backports commit 07b001c6fc500fa0e87fd8210f270d7dc8aff9ea from qemu
2019-03-19 08:50:05 +00:00
%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
%imm_lui 12:s1 2:5 !function=ex_shift_12
target/riscv: Convert quadrant 0 of RVXC insns to decodetree
2019-03-19 08:45:40 +00:00
target/riscv: Merge argument sets for insn32 and insn16 In some cases this allows us to directly use the insn32 translator function. In some cases we still need a shim. Backports commit e1d455dd91c935c714412dafeb24db947429a929 from qemu
2019-05-28 22:48:16 +00:00
# Argument sets imported from insn32.decode:
&empty !extern
&r rd rs1 rs2 !extern
&i imm rs1 rd !extern
&s imm rs1 rs2 !extern
&j imm rd !extern
&b imm rs2 rs1 !extern
&u imm rd !extern
&shift shamt rs1 rd !extern
target/riscv: Convert quadrant 0 of RVXC insns to decodetree
2019-03-19 08:45:40 +00:00
# Formats 16:
target/riscv: Merge argument sets for insn32 and insn16 In some cases this allows us to directly use the insn32 translator function. In some cases we still need a shim. Backports commit e1d455dd91c935c714412dafeb24db947429a929 from qemu
2019-05-28 22:48:16 +00:00
@cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
@ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd
@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
@cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3
@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
@cj ... ........... .. &j imm=%imm_cj
@cb_z ... ... ... .. ... .. &b imm=%imm_cb rs1=%rs1_3 rs2=0
@c_ldsp ... . ..... ..... .. &i imm=%uimm_6bit_ld rs1=2 %rd
@c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd
@c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
@c_swsp ... . ..... ..... .. &s imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5
@c_li ... . ..... ..... .. &i imm=%imm_ci rs1=0 %rd
target/riscv: Use pattern groups in insn16.decode This eliminates about half of the complicated decode bits within insn_trans/trans_rvc.inc.c. Backports commit c2cfb97c01a3636867c1a4a24f8a99fd8c6bed28 from qemu
2019-05-28 22:55:26 +00:00
@c_lui ... . ..... ..... .. &u imm=%imm_lui %rd
@c_jalr ... . ..... ..... .. &i imm=0 rs1=%rd
@c_mv ... . ..... ..... .. &i imm=0 rs1=%rs2_5 %rd
target/riscv: Convert quadrant 2 of RVXC insns to decodetree Backports commit 97b0be81f6f20bfd53725cb2500b47c6786be532 from qemu
2019-03-19 08:53:05 +00:00
target/riscv: Use pattern groups in insn16.decode This eliminates about half of the complicated decode bits within insn_trans/trans_rvc.inc.c. Backports commit c2cfb97c01a3636867c1a4a24f8a99fd8c6bed28 from qemu
2019-05-28 22:55:26 +00:00
@c_addi4spn ... . ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
@c_addi16sp ... . ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2
target/riscv: Convert quadrant 1 of RVXC insns to decodetree Backports commit 07b001c6fc500fa0e87fd8210f270d7dc8aff9ea from qemu
2019-03-19 08:50:05 +00:00
target/riscv: Merge argument sets for insn32 and insn16 In some cases this allows us to directly use the insn32 translator function. In some cases we still need a shim. Backports commit e1d455dd91c935c714412dafeb24db947429a929 from qemu
2019-05-28 22:48:16 +00:00
@c_shift ... . .. ... ..... .. \
target/riscv: Merge argument decode for RVC shifti Special handling for IMM==0 is the only difference between RVC shifti and RVI shifti. This can be handled with !function. Backports commit 6cafec92f1c862a9754ef6a28be68ba7178a284d from qemu
2019-05-28 22:52:47 +00:00
&shift rd=%rs1_3 rs1=%rs1_3 shamt=%shimm_6bit
target/riscv: Merge argument sets for insn32 and insn16 In some cases this allows us to directly use the insn32 translator function. In some cases we still need a shim. Backports commit e1d455dd91c935c714412dafeb24db947429a929 from qemu
2019-05-28 22:48:16 +00:00
@c_shift2 ... . .. ... ..... .. \
target/riscv: Merge argument decode for RVC shifti Special handling for IMM==0 is the only difference between RVC shifti and RVI shifti. This can be handled with !function. Backports commit 6cafec92f1c862a9754ef6a28be68ba7178a284d from qemu
2019-05-28 22:52:47 +00:00
&shift rd=%rd rs1=%rd shamt=%shimm_6bit
target/riscv: Convert quadrant 1 of RVXC insns to decodetree Backports commit 07b001c6fc500fa0e87fd8210f270d7dc8aff9ea from qemu
2019-03-19 08:50:05 +00:00
target/riscv: Merge argument sets for insn32 and insn16 In some cases this allows us to directly use the insn32 translator function. In some cases we still need a shim. Backports commit e1d455dd91c935c714412dafeb24db947429a929 from qemu
2019-05-28 22:48:16 +00:00
@c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
target/riscv: Convert quadrant 0 of RVXC insns to decodetree
2019-03-19 08:45:40 +00:00
target/riscv: Split RVC32 and RVC64 insns into separate files This eliminates all functions in insn_trans/trans_rvc.inc.c, so the entire file can be removed. Backports commit 0e68e240a9bd3b44a91cd6012f0e2bf2a43b9fe2 from qemu
2019-05-28 23:00:20 +00:00
# *** RV32/64C Standard Extension (Quadrant 0) ***
target/riscv: Use pattern groups in insn16.decode This eliminates about half of the complicated decode bits within insn_trans/trans_rvc.inc.c. Backports commit c2cfb97c01a3636867c1a4a24f8a99fd8c6bed28 from qemu
2019-05-28 22:55:26 +00:00
{
# Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
illegal 000 000 000 00 --- 00
addi 000 ... ... .. ... 00 @c_addi4spn
}
target/riscv: Merge argument sets for insn32 and insn16 In some cases this allows us to directly use the insn32 translator function. In some cases we still need a shim. Backports commit e1d455dd91c935c714412dafeb24db947429a929 from qemu
2019-05-28 22:48:16 +00:00
fld 001 ... ... .. ... 00 @cl_d
lw 010 ... ... .. ... 00 @cl_w
fsd 101 ... ... .. ... 00 @cs_d
sw 110 ... ... .. ... 00 @cs_w
target/riscv: Convert quadrant 1 of RVXC insns to decodetree Backports commit 07b001c6fc500fa0e87fd8210f270d7dc8aff9ea from qemu
2019-03-19 08:50:05 +00:00
target/riscv: Split RVC32 and RVC64 insns into separate files This eliminates all functions in insn_trans/trans_rvc.inc.c, so the entire file can be removed. Backports commit 0e68e240a9bd3b44a91cd6012f0e2bf2a43b9fe2 from qemu
2019-05-28 23:00:20 +00:00
# *** RV32/64C Standard Extension (Quadrant 1) ***
target/riscv: Merge argument sets for insn32 and insn16 In some cases this allows us to directly use the insn32 translator function. In some cases we still need a shim. Backports commit e1d455dd91c935c714412dafeb24db947429a929 from qemu
2019-05-28 22:48:16 +00:00
addi 000 . ..... ..... 01 @ci
addi 010 . ..... ..... 01 @c_li
target/riscv: Use pattern groups in insn16.decode This eliminates about half of the complicated decode bits within insn_trans/trans_rvc.inc.c. Backports commit c2cfb97c01a3636867c1a4a24f8a99fd8c6bed28 from qemu
2019-05-28 22:55:26 +00:00
{
target/riscv: Add checks for several RVC reserved operands C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved operands that were not diagnosed. Backports commit 4cc16b3b9282e04fab8e84d136540757e82af019 from qemu
2019-05-28 23:20:21 +00:00
illegal 011 0 ----- 00000 01 # c.addi16sp and c.lui, RES nzimm=0
target/riscv: Use pattern groups in insn16.decode This eliminates about half of the complicated decode bits within insn_trans/trans_rvc.inc.c. Backports commit c2cfb97c01a3636867c1a4a24f8a99fd8c6bed28 from qemu
2019-05-28 22:55:26 +00:00
addi 011 . 00010 ..... 01 @c_addi16sp
lui 011 . ..... ..... 01 @c_lui
}
target/riscv: Merge argument decode for RVC shifti Special handling for IMM==0 is the only difference between RVC shifti and RVI shifti. This can be handled with !function. Backports commit 6cafec92f1c862a9754ef6a28be68ba7178a284d from qemu
2019-05-28 22:52:47 +00:00
srli 100 . 00 ... ..... 01 @c_shift
srai 100 . 01 ... ..... 01 @c_shift
target/riscv: Merge argument sets for insn32 and insn16 In some cases this allows us to directly use the insn32 translator function. In some cases we still need a shim. Backports commit e1d455dd91c935c714412dafeb24db947429a929 from qemu
2019-05-28 22:48:16 +00:00
andi 100 . 10 ... ..... 01 @c_andi
sub 100 0 11 ... 00 ... 01 @cs_2
xor 100 0 11 ... 01 ... 01 @cs_2
or 100 0 11 ... 10 ... 01 @cs_2
and 100 0 11 ... 11 ... 01 @cs_2
jal 101 ........... 01 @cj rd=0 # C.J
beq 110 ... ... ..... 01 @cb_z
bne 111 ... ... ..... 01 @cb_z
target/riscv: Convert quadrant 2 of RVXC insns to decodetree Backports commit 97b0be81f6f20bfd53725cb2500b47c6786be532 from qemu
2019-03-19 08:53:05 +00:00
target/riscv: Split RVC32 and RVC64 insns into separate files This eliminates all functions in insn_trans/trans_rvc.inc.c, so the entire file can be removed. Backports commit 0e68e240a9bd3b44a91cd6012f0e2bf2a43b9fe2 from qemu
2019-05-28 23:00:20 +00:00
# *** RV32/64C Standard Extension (Quadrant 2) ***
target/riscv: Merge argument decode for RVC shifti Special handling for IMM==0 is the only difference between RVC shifti and RVI shifti. This can be handled with !function. Backports commit 6cafec92f1c862a9754ef6a28be68ba7178a284d from qemu
2019-05-28 22:52:47 +00:00
slli 000 . ..... ..... 10 @c_shift2
target/riscv: Merge argument sets for insn32 and insn16 In some cases this allows us to directly use the insn32 translator function. In some cases we still need a shim. Backports commit e1d455dd91c935c714412dafeb24db947429a929 from qemu
2019-05-28 22:48:16 +00:00
fld 001 . ..... ..... 10 @c_ldsp
target/riscv: Use pattern groups in insn16.decode This eliminates about half of the complicated decode bits within insn_trans/trans_rvc.inc.c. Backports commit c2cfb97c01a3636867c1a4a24f8a99fd8c6bed28 from qemu
2019-05-28 22:55:26 +00:00
{
target/riscv: Add checks for several RVC reserved operands C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved operands that were not diagnosed. Backports commit 4cc16b3b9282e04fab8e84d136540757e82af019 from qemu
2019-05-28 23:20:21 +00:00
illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0
lw 010 . ..... ..... 10 @c_lwsp
}
{
illegal 100 0 00000 00000 10 # c.jr, RES rs1=0
target/riscv: Use pattern groups in insn16.decode This eliminates about half of the complicated decode bits within insn_trans/trans_rvc.inc.c. Backports commit c2cfb97c01a3636867c1a4a24f8a99fd8c6bed28 from qemu
2019-05-28 22:55:26 +00:00
jalr 100 0 ..... 00000 10 @c_jalr rd=0 # C.JR
addi 100 0 ..... ..... 10 @c_mv
}
{
ebreak 100 1 00000 00000 10
jalr 100 1 ..... 00000 10 @c_jalr rd=1 # C.JALR
add 100 1 ..... ..... 10 @cr
}
target/riscv: Merge argument sets for insn32 and insn16 In some cases this allows us to directly use the insn32 translator function. In some cases we still need a shim. Backports commit e1d455dd91c935c714412dafeb24db947429a929 from qemu
2019-05-28 22:48:16 +00:00
fsd 101 ...... ..... 10 @c_sdsp
sw 110 . ..... ..... 10 @c_swsp
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