2015-08-21 07:04:50 +00:00
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#ifndef TARGET_ARM_TRANSLATE_H
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#define TARGET_ARM_TRANSLATE_H
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2018-03-04 18:58:56 +00:00
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#include "exec/translator.h"
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2015-08-21 07:04:50 +00:00
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/* internal defines */
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typedef struct DisasContext {
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2018-03-04 22:54:11 +00:00
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DisasContextBase base;
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2018-11-10 13:17:52 +00:00
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const ARMISARegisters *isar;
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2018-03-05 00:40:51 +00:00
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2015-08-21 07:04:50 +00:00
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target_ulong pc;
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2018-05-11 17:47:17 +00:00
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target_ulong page_start;
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2015-08-21 07:04:50 +00:00
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uint32_t insn;
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/* Nonzero if this instruction has been conditionally skipped. */
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int condjmp;
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/* The label that will be jumped to when the instruction is skipped. */
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2018-02-09 19:10:32 +00:00
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TCGLabel *condlabel;
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2015-08-21 07:04:50 +00:00
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/* Thumb-2 conditional execution bits. */
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int condexec_mask;
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int condexec_cond;
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int thumb;
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2018-02-21 07:04:31 +00:00
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int sctlr_b;
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2018-02-21 07:20:42 +00:00
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TCGMemOp be_data;
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2015-08-21 07:04:50 +00:00
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#if !defined(CONFIG_USER_ONLY)
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int user;
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#endif
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2018-02-12 16:13:11 +00:00
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ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
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2018-02-26 12:58:04 +00:00
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bool tbi0; /* TBI0 for EL0/1 or TBI for EL2/3 */
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bool tbi1; /* TBI1 for EL0/1, not used for EL2/3 */
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2018-02-11 22:48:50 +00:00
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bool ns; /* Use non-secure CPREG bank on access */
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2018-02-13 04:03:55 +00:00
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int fp_excp_el; /* FP exception EL or 0 if enabled */
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2018-03-07 16:44:30 +00:00
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int sve_excp_el; /* SVE exception EL or 0 if enabled */
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int sve_len; /* SVE vector length in bytes */
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2018-02-15 16:15:49 +00:00
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/* Flag indicating that exceptions from secure mode are routed to EL3. */
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bool secure_routed_to_el3;
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2015-08-21 07:04:50 +00:00
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bool vfp_enabled; /* FP enabled via FPSCR.EN */
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int vec_len;
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int vec_stride;
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2018-03-02 19:54:13 +00:00
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bool v7m_handler_mode;
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2018-03-05 02:18:56 +00:00
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bool v8m_secure; /* true if v8M and we're in Secure mode */
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2018-10-08 17:46:38 +00:00
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bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */
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2015-08-21 07:04:50 +00:00
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/* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
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* so that top level loop can generate correct syndrome information.
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*/
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uint32_t svc_imm;
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int aarch64;
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int current_el;
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GHashTable *cp_regs;
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uint64_t features; /* CPU features bits */
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/* Because unallocated encodings generate different exception syndrome
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* information from traps due to FP being disabled, we can't do a single
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* "is fp access disabled" check at a high level in the decode tree.
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* To help in catching bugs where the access check was forgotten in some
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* code path, we set this flag when the access check is done, and assert
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* that it is set at the point where we actually touch the FP regs.
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*/
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bool fp_access_checked;
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/* ARMv8 single-step state (this is distinct from the QEMU gdbstub
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* single-step support).
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*/
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bool ss_active;
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bool pstate_ss;
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/* True if the insn just emitted was a load-exclusive instruction
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* (necessary for syndrome information for single step exceptions),
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* ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
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*/
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bool is_ldex;
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/* True if a single-step exception will be taken to the current EL */
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bool ss_same_el;
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/* Bottom two bits of XScale c15_cpar coprocessor access control reg */
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int c15_cpar;
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2018-03-05 21:01:13 +00:00
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/* TCG op of the current insn_start. */
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TCGOp *insn_start;
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2015-08-21 07:04:50 +00:00
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#define TMP_A64_MAX 16
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int tmp_a64_count;
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TCGv_i64 tmp_a64[TMP_A64_MAX];
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2018-10-06 07:31:27 +00:00
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// Unicorn: Moved here to avoid global state.
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2018-10-06 07:26:52 +00:00
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TCGv_i64 V0;
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2018-10-06 07:28:42 +00:00
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TCGv_i64 V1;
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2018-10-06 07:31:27 +00:00
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TCGv_i64 M0;
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2018-10-06 06:58:03 +00:00
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TCGv_i32 F0s;
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2018-10-06 07:02:06 +00:00
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TCGv_i32 F1s;
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2018-10-06 07:05:34 +00:00
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TCGv_i64 F0d;
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2018-10-06 07:11:52 +00:00
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TCGv_i64 F1d;
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2018-10-06 06:58:03 +00:00
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2015-08-21 07:04:50 +00:00
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// Unicorn engine
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struct uc_struct *uc;
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} DisasContext;
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2018-02-11 04:42:08 +00:00
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typedef struct DisasCompare {
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TCGCond cond;
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TCGv_i32 value;
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bool value_global;
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} DisasCompare;
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2015-08-21 07:04:50 +00:00
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static inline int arm_dc_feature(DisasContext *dc, int feature)
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{
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return (dc->features & (1ULL << feature)) != 0;
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}
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static inline int get_mem_index(DisasContext *s)
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{
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2018-03-02 20:35:47 +00:00
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return arm_to_core_mmu_idx(s->mmu_idx);
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2015-08-21 07:04:50 +00:00
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}
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2018-02-13 03:08:30 +00:00
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/* Function used to determine the target exception EL when otherwise not known
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* or default.
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*/
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static inline int default_exception_el(DisasContext *s)
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{
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/* If we are coming from secure EL0 in a system with a 32-bit EL3, then
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* there is no secure EL1, so we route exceptions to EL3. Otherwise,
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* exceptions can only be routed to ELs above 1, so we target the higher of
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* 1 or the current EL.
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*/
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2018-02-15 16:15:49 +00:00
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return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3)
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2018-02-13 03:08:30 +00:00
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? 3 : MAX(1, s->current_el);
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}
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2018-03-06 14:19:58 +00:00
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static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
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2018-03-02 05:36:06 +00:00
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{
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/* We don't need to save all of the syndrome so we mask and shift
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* out unneeded bits to help the sleb128 encoder do a better job.
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*/
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syn &= ARM_INSN_START_WORD2_MASK;
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syn >>= ARM_INSN_START_WORD2_SHIFT;
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/* We check and clear insn_start_idx to catch multiple updates. */
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2018-03-05 21:01:13 +00:00
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assert(s->insn_start != NULL);
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2018-04-11 23:33:23 +00:00
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tcg_set_insn_start_param(s->insn_start, 2, syn);
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2018-03-05 21:01:13 +00:00
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s->insn_start = NULL;
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2018-03-02 05:36:06 +00:00
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}
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2015-08-21 07:04:50 +00:00
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/* target-specific extra values for is_jmp */
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2018-03-04 18:58:56 +00:00
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/* is_jmp field values */
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#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
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#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
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2015-08-21 07:04:50 +00:00
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/* These instructions trap after executing, so the A32/T32 decoder must
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* defer them until after the conditional execution state has been updated.
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* WFI also needs special handling when single-stepping.
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*/
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2018-03-04 18:58:56 +00:00
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#define DISAS_WFI DISAS_TARGET_2
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#define DISAS_SWI DISAS_TARGET_3
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2015-08-21 07:04:50 +00:00
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/* WFE */
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2018-03-04 18:58:56 +00:00
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#define DISAS_WFE DISAS_TARGET_4
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#define DISAS_HVC DISAS_TARGET_5
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#define DISAS_SMC DISAS_TARGET_6
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#define DISAS_YIELD DISAS_TARGET_7
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arm: Implement M profile exception return properly
On M profile, return from exceptions happen when code in Handler mode
executes one of the following function call return instructions:
* POP or LDM which loads the PC
* LDR to PC
* BX register
and the new PC value is 0xFFxxxxxx.
QEMU tries to implement this by not treating the instruction
specially but then catching the attempt to execute from the magic
address value. This is not ideal, because:
* there are guest visible differences from the architecturally
specified behaviour (for instance jumping to 0xFFxxxxxx via a
different instruction should not cause an exception return but it
will in the QEMU implementation)
* we have to account for it in various places (like refusing to take
an interrupt if the PC is at a magic value, and making sure that
the MPU doesn't deny execution at the magic value addresses)
Drop these hacks, and instead implement exception return the way the
architecture specifies -- by having the relevant instructions check
for the magic value and raise the 'do an exception return' QEMU
internal exception immediately.
The effect on the generated code is minor:
bx lr, old code (and new code for Thread mode):
TCG:
mov_i32 tmp5,r14
movi_i32 tmp6,$0xfffffffffffffffe
and_i32 pc,tmp5,tmp6
movi_i32 tmp6,$0x1
and_i32 tmp5,tmp5,tmp6
st_i32 tmp5,env,$0x218
exit_tb $0x0
set_label $L0
exit_tb $0x7f2aabd61993
x86_64 generated code:
0x7f2aabe87019: mov %ebx,%ebp
0x7f2aabe8701b: and $0xfffffffffffffffe,%ebp
0x7f2aabe8701e: mov %ebp,0x3c(%r14)
0x7f2aabe87022: and $0x1,%ebx
0x7f2aabe87025: mov %ebx,0x218(%r14)
0x7f2aabe8702c: xor %eax,%eax
0x7f2aabe8702e: jmpq 0x7f2aabe7c016
bx lr, new code when in Handler mode:
TCG:
mov_i32 tmp5,r14
movi_i32 tmp6,$0xfffffffffffffffe
and_i32 pc,tmp5,tmp6
movi_i32 tmp6,$0x1
and_i32 tmp5,tmp5,tmp6
st_i32 tmp5,env,$0x218
movi_i32 tmp5,$0xffffffffff000000
brcond_i32 pc,tmp5,geu,$L1
exit_tb $0x0
set_label $L1
movi_i32 tmp5,$0x8
call exception_internal,$0x0,$0,env,tmp5
x86_64 generated code:
0x7fe8fa1264e3: mov %ebp,%ebx
0x7fe8fa1264e5: and $0xfffffffffffffffe,%ebx
0x7fe8fa1264e8: mov %ebx,0x3c(%r14)
0x7fe8fa1264ec: and $0x1,%ebp
0x7fe8fa1264ef: mov %ebp,0x218(%r14)
0x7fe8fa1264f6: cmp $0xff000000,%ebx
0x7fe8fa1264fc: jae 0x7fe8fa126509
0x7fe8fa126502: xor %eax,%eax
0x7fe8fa126504: jmpq 0x7fe8fa122016
0x7fe8fa126509: mov %r14,%rdi
0x7fe8fa12650c: mov $0x8,%esi
0x7fe8fa126511: mov $0x56095dbeccf5,%r10
0x7fe8fa12651b: callq *%r10
which is a difference of one cmp/branch-not-taken. This will
be lost in the noise of having to exit generated code and
look up the next TB anyway.
Backports commit 3bb8a96f5348913ee130169504f3642f501b113e from qemu
2018-03-02 19:56:27 +00:00
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/* M profile branch which might be an exception return (and so needs
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* custom end-of-TB code)
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*/
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2018-03-04 18:58:56 +00:00
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#define DISAS_BX_EXCRET DISAS_TARGET_8
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2018-03-03 02:16:56 +00:00
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/* For instructions which want an immediate exit to the main loop,
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2018-03-04 03:36:22 +00:00
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* as opposed to attempting to use lookup_and_goto_ptr. Unlike
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* DISAS_UPDATE this doesn't write the PC on exiting the translation
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* loop so you need to ensure something (gen_a64_set_pc_im or runtime
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* helper) has done so before we reach return from cpu_tb_exec.
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2018-03-03 02:16:56 +00:00
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*/
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2018-03-04 18:58:56 +00:00
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#define DISAS_EXIT DISAS_TARGET_9
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2015-08-21 07:04:50 +00:00
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#ifdef TARGET_AARCH64
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void a64_translate_init(struct uc_struct *uc);
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void gen_a64_set_pc_im(DisasContext *s, uint64_t val);
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2018-03-05 01:11:49 +00:00
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extern const TranslatorOps aarch64_translator_ops;
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2015-08-21 07:04:50 +00:00
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#else
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static inline void a64_translate_init(struct uc_struct *uc)
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{
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}
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2018-03-04 03:32:59 +00:00
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static inline void gen_a64_set_pc_im(DisasContext *s, uint64_t val)
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2015-08-21 07:04:50 +00:00
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{
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}
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#endif
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2018-10-06 07:45:49 +00:00
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void arm_test_cc(DisasContext *s, DisasCompare *cmp, int cc);
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void arm_free_cc(DisasContext *s, DisasCompare *cmp);
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void arm_jump_cc(DisasContext *s, DisasCompare *cmp, TCGLabel *label);
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void arm_gen_test_cc(DisasContext *s, int cc, TCGLabel *label);
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2015-08-21 07:04:50 +00:00
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2018-05-20 02:33:49 +00:00
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/* Return state of Alternate Half-precision flag, caller frees result */
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2018-10-06 07:45:49 +00:00
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static inline TCGv_i32 get_ahp_flag(DisasContext *s)
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2018-05-20 02:33:49 +00:00
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{
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2018-10-06 07:45:49 +00:00
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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2018-05-20 02:33:49 +00:00
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TCGv_i32 ret = tcg_temp_new_i32(tcg_ctx);
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tcg_gen_ld_i32(tcg_ctx, ret, tcg_ctx->cpu_env,
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offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
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tcg_gen_extract_i32(tcg_ctx, ret, ret, 26, 1);
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return ret;
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}
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2018-11-10 15:04:28 +00:00
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/* Vector operations shared between ARM and AArch64. */
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extern const GVecGen3 bsl_op;
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extern const GVecGen3 bit_op;
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extern const GVecGen3 bif_op;
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2018-11-10 15:32:29 +00:00
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extern const GVecGen2i ssra_op[4];
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extern const GVecGen2i usra_op[4];
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2018-11-10 15:04:28 +00:00
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2018-11-10 13:17:52 +00:00
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/*
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* Forward to the isar_feature_* tests given a DisasContext pointer.
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*/
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#define dc_isar_feature(name, ctx) \
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({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
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2015-08-21 07:04:50 +00:00
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#endif /* TARGET_ARM_TRANSLATE_H */
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