2019-06-13 20:24:24 +00:00
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/*
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* ARM translation: AArch32 VFP instructions
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2005-2007 CodeSourcery
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* Copyright (c) 2007 OpenedHand, Ltd.
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* Copyright (c) 2019 Linaro, Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* This file is intended to be included from translate.c; it uses
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* some macros and definitions provided by that file.
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* It might be possible to convert it to a standalone .c file eventually.
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*/
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/* Include the generated VFP decoder */
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#include "decode-vfp.inc.c"
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#include "decode-vfp-uncond.inc.c"
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2019-06-13 20:30:12 +00:00
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/*
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* Check that VFP access is enabled. If it is, do the necessary
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* M-profile lazy-FP handling and then return true.
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* If not, emit code to generate an appropriate exception and
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* return false.
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* The ignore_vfp_enabled argument specifies that we should ignore
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* whether VFP is enabled via FPEXC[EN]: this should be true for FMXR/FMRX
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* accesses to FPSID, FPEXC, MVFR0, MVFR1, MVFR2, and false for all other insns.
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*/
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static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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if (s->fp_excp_el) {
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if (arm_dc_feature(s, ARM_FEATURE_M)) {
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gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(),
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s->fp_excp_el);
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} else {
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gen_exception_insn(s, 4, EXCP_UDEF,
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syn_fp_access_trap(1, 0xe, false),
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s->fp_excp_el);
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}
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return false;
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}
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if (!s->vfp_enabled && !ignore_vfp_enabled) {
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assert(!arm_dc_feature(s, ARM_FEATURE_M));
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gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
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default_exception_el(s));
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return false;
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}
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if (arm_dc_feature(s, ARM_FEATURE_M)) {
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/* Handle M-profile lazy FP state mechanics */
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/* Trigger lazy-state preservation if necessary */
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if (s->v7m_lspact) {
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/*
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* Lazy state saving affects external memory and also the NVIC,
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* so we must mark it as an IO operation for icount.
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*/
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if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
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gen_io_start(tcg_ctx);
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}
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gen_helper_v7m_preserve_fp_state(tcg_ctx, tcg_ctx->cpu_env);
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if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
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gen_io_end(tcg_ctx);
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}
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/*
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* If the preserve_fp_state helper doesn't throw an exception
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* then it will clear LSPACT; we don't need to repeat this for
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* any further FP insns in this TB.
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*/
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s->v7m_lspact = false;
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}
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/* Update ownership of FP context: set FPCCR.S to match current state */
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if (s->v8m_fpccr_s_wrong) {
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TCGv_i32 tmp;
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2019-06-13 20:35:30 +00:00
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tmp = load_cpu_field(s, v7m.fpccr[M_REG_S]);
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2019-06-13 20:30:12 +00:00
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if (s->v8m_secure) {
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tcg_gen_ori_i32(tcg_ctx, tmp, tmp, R_V7M_FPCCR_S_MASK);
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} else {
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tcg_gen_andi_i32(tcg_ctx, tmp, tmp, ~R_V7M_FPCCR_S_MASK);
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}
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store_cpu_field(s, tmp, v7m.fpccr[M_REG_S]);
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/* Don't need to do this for any further FP insns in this TB */
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s->v8m_fpccr_s_wrong = false;
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}
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if (s->v7m_new_fp_ctxt_needed) {
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/*
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* Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA
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* and the FPSCR.
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*/
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TCGv_i32 control, fpscr;
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uint32_t bits = R_V7M_CONTROL_FPCA_MASK;
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2019-06-13 20:35:30 +00:00
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fpscr = load_cpu_field(s, v7m.fpdscr[s->v8m_secure]);
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2019-06-13 20:30:12 +00:00
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gen_helper_vfp_set_fpscr(tcg_ctx, tcg_ctx->cpu_env, fpscr);
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tcg_temp_free_i32(tcg_ctx, fpscr);
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/*
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* We don't need to arrange to end the TB, because the only
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* parts of FPSCR which we cache in the TB flags are the VECLEN
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* and VECSTRIDE, and those don't exist for M-profile.
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*/
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if (s->v8m_secure) {
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bits |= R_V7M_CONTROL_SFPA_MASK;
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}
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2019-06-13 20:35:30 +00:00
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control = load_cpu_field(s, v7m.control[M_REG_S]);
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2019-06-13 20:30:12 +00:00
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tcg_gen_ori_i32(tcg_ctx, control, control, bits);
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store_cpu_field(s, control, v7m.control[M_REG_S]);
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/* Don't need to do this for any further FP insns in this TB */
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s->v7m_new_fp_ctxt_needed = false;
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}
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}
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return true;
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}
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2019-06-13 20:41:19 +00:00
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/*
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* The most usual kind of VFP access check, for everything except
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* FMXR/FMRX to the always-available special registers.
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*/
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static bool vfp_access_check(DisasContext *s)
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{
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return full_vfp_access_check(s, false);
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}
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2019-06-13 20:56:21 +00:00
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static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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uint32_t rd, rn, rm;
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bool dp = a->dp;
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if (!dc_isar_feature(aa32_vsel, s)) {
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist */
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if (dp && !dc_isar_feature(aa32_fp_d32, s) &&
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((a->vm | a->vn | a->vd) & 0x10)) {
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return false;
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}
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rd = a->vd;
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rn = a->vn;
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rm = a->vm;
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if (!vfp_access_check(s)) {
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return true;
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}
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if (dp) {
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TCGv_i64 frn, frm, dest;
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TCGv_i64 tmp, zero, zf, nf, vf;
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zero = tcg_const_i64(tcg_ctx, 0);
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frn = tcg_temp_new_i64(tcg_ctx);
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frm = tcg_temp_new_i64(tcg_ctx);
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dest = tcg_temp_new_i64(tcg_ctx);
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zf = tcg_temp_new_i64(tcg_ctx);
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nf = tcg_temp_new_i64(tcg_ctx);
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vf = tcg_temp_new_i64(tcg_ctx);
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tcg_gen_extu_i32_i64(tcg_ctx, zf, tcg_ctx->cpu_ZF);
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tcg_gen_ext_i32_i64(tcg_ctx, nf, tcg_ctx->cpu_NF);
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tcg_gen_ext_i32_i64(tcg_ctx, vf, tcg_ctx->cpu_VF);
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target/arm: Add helpers for VFP register loads and stores
The current VFP code has two different idioms for
loading and storing from the VFP register file:
1 using the gen_mov_F0_vreg() and similar functions,
which load and store to a fixed set of TCG globals
cpu_F0s, CPU_F0d, etc
2 by direct calls to tcg_gen_ld_f64() and friends
We want to phase out idiom 1 (because the use of the
fixed globals is a relic of a much older version of TCG),
but idiom 2 is quite longwinded:
tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg))
requires us to specify the 64-bitness twice, once in
the function name and once by passing 'true' to
vfp_reg_offset(). There's no guard against accidentally
passing the wrong flag.
Instead, let's move to a convention of accessing 64-bit
registers via the existing neon_load_reg64() and
neon_store_reg64(), and provide new neon_load_reg32()
and neon_store_reg32() for the 32-bit equivalents.
Implement the new functions and use them in the code in
translate-vfp.inc.c. We will convert the rest of the VFP
code as we do the decodetree conversion in subsequent
commits.
Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
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neon_load_reg64(s, frn, rn);
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neon_load_reg64(s, frm, rm);
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2019-06-13 20:56:21 +00:00
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switch (a->cc) {
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case 0: /* eq: Z */
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tcg_gen_movcond_i64(tcg_ctx, TCG_COND_EQ, dest, zf, zero,
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frn, frm);
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break;
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case 1: /* vs: V */
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tcg_gen_movcond_i64(tcg_ctx, TCG_COND_LT, dest, vf, zero,
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frn, frm);
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break;
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case 2: /* ge: N == V -> N ^ V == 0 */
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tmp = tcg_temp_new_i64(tcg_ctx);
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tcg_gen_xor_i64(tcg_ctx, tmp, vf, nf);
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tcg_gen_movcond_i64(tcg_ctx, TCG_COND_GE, dest, tmp, zero,
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frn, frm);
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tcg_temp_free_i64(tcg_ctx, tmp);
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break;
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case 3: /* gt: !Z && N == V */
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tcg_gen_movcond_i64(tcg_ctx, TCG_COND_NE, dest, zf, zero,
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frn, frm);
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tmp = tcg_temp_new_i64(tcg_ctx);
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tcg_gen_xor_i64(tcg_ctx, tmp, vf, nf);
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tcg_gen_movcond_i64(tcg_ctx, TCG_COND_GE, dest, tmp, zero,
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dest, frm);
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tcg_temp_free_i64(tcg_ctx, tmp);
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break;
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}
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target/arm: Add helpers for VFP register loads and stores
The current VFP code has two different idioms for
loading and storing from the VFP register file:
1 using the gen_mov_F0_vreg() and similar functions,
which load and store to a fixed set of TCG globals
cpu_F0s, CPU_F0d, etc
2 by direct calls to tcg_gen_ld_f64() and friends
We want to phase out idiom 1 (because the use of the
fixed globals is a relic of a much older version of TCG),
but idiom 2 is quite longwinded:
tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg))
requires us to specify the 64-bitness twice, once in
the function name and once by passing 'true' to
vfp_reg_offset(). There's no guard against accidentally
passing the wrong flag.
Instead, let's move to a convention of accessing 64-bit
registers via the existing neon_load_reg64() and
neon_store_reg64(), and provide new neon_load_reg32()
and neon_store_reg32() for the 32-bit equivalents.
Implement the new functions and use them in the code in
translate-vfp.inc.c. We will convert the rest of the VFP
code as we do the decodetree conversion in subsequent
commits.
Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
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neon_store_reg64(s, dest, rd);
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2019-06-13 20:56:21 +00:00
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tcg_temp_free_i64(tcg_ctx, frn);
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tcg_temp_free_i64(tcg_ctx, frm);
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tcg_temp_free_i64(tcg_ctx, dest);
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tcg_temp_free_i64(tcg_ctx, zf);
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tcg_temp_free_i64(tcg_ctx, nf);
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tcg_temp_free_i64(tcg_ctx, vf);
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tcg_temp_free_i64(tcg_ctx, zero);
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} else {
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TCGv_i32 frn, frm, dest;
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TCGv_i32 tmp, zero;
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zero = tcg_const_i32(tcg_ctx, 0);
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frn = tcg_temp_new_i32(tcg_ctx);
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frm = tcg_temp_new_i32(tcg_ctx);
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dest = tcg_temp_new_i32(tcg_ctx);
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target/arm: Add helpers for VFP register loads and stores
The current VFP code has two different idioms for
loading and storing from the VFP register file:
1 using the gen_mov_F0_vreg() and similar functions,
which load and store to a fixed set of TCG globals
cpu_F0s, CPU_F0d, etc
2 by direct calls to tcg_gen_ld_f64() and friends
We want to phase out idiom 1 (because the use of the
fixed globals is a relic of a much older version of TCG),
but idiom 2 is quite longwinded:
tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg))
requires us to specify the 64-bitness twice, once in
the function name and once by passing 'true' to
vfp_reg_offset(). There's no guard against accidentally
passing the wrong flag.
Instead, let's move to a convention of accessing 64-bit
registers via the existing neon_load_reg64() and
neon_store_reg64(), and provide new neon_load_reg32()
and neon_store_reg32() for the 32-bit equivalents.
Implement the new functions and use them in the code in
translate-vfp.inc.c. We will convert the rest of the VFP
code as we do the decodetree conversion in subsequent
commits.
Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
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neon_load_reg32(s, frn, rn);
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neon_load_reg32(s, frm, rm);
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2019-06-13 20:56:21 +00:00
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switch (a->cc) {
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case 0: /* eq: Z */
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tcg_gen_movcond_i32(tcg_ctx, TCG_COND_EQ, dest, tcg_ctx->cpu_ZF, zero,
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frn, frm);
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break;
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case 1: /* vs: V */
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tcg_gen_movcond_i32(tcg_ctx, TCG_COND_LT, dest, tcg_ctx->cpu_VF, zero,
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frn, frm);
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break;
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case 2: /* ge: N == V -> N ^ V == 0 */
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tmp = tcg_temp_new_i32(tcg_ctx);
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tcg_gen_xor_i32(tcg_ctx, tmp, tcg_ctx->cpu_VF, tcg_ctx->cpu_NF);
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tcg_gen_movcond_i32(tcg_ctx, TCG_COND_GE, dest, tmp, zero,
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frn, frm);
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tcg_temp_free_i32(tcg_ctx, tmp);
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break;
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case 3: /* gt: !Z && N == V */
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tcg_gen_movcond_i32(tcg_ctx, TCG_COND_NE, dest, tcg_ctx->cpu_ZF, zero,
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frn, frm);
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tmp = tcg_temp_new_i32(tcg_ctx);
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tcg_gen_xor_i32(tcg_ctx, tmp, tcg_ctx->cpu_VF, tcg_ctx->cpu_NF);
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tcg_gen_movcond_i32(tcg_ctx, TCG_COND_GE, dest, tmp, zero,
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dest, frm);
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tcg_temp_free_i32(tcg_ctx, tmp);
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break;
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}
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target/arm: Add helpers for VFP register loads and stores
The current VFP code has two different idioms for
loading and storing from the VFP register file:
1 using the gen_mov_F0_vreg() and similar functions,
which load and store to a fixed set of TCG globals
cpu_F0s, CPU_F0d, etc
2 by direct calls to tcg_gen_ld_f64() and friends
We want to phase out idiom 1 (because the use of the
fixed globals is a relic of a much older version of TCG),
but idiom 2 is quite longwinded:
tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg))
requires us to specify the 64-bitness twice, once in
the function name and once by passing 'true' to
vfp_reg_offset(). There's no guard against accidentally
passing the wrong flag.
Instead, let's move to a convention of accessing 64-bit
registers via the existing neon_load_reg64() and
neon_store_reg64(), and provide new neon_load_reg32()
and neon_store_reg32() for the 32-bit equivalents.
Implement the new functions and use them in the code in
translate-vfp.inc.c. We will convert the rest of the VFP
code as we do the decodetree conversion in subsequent
commits.
Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
|
|
|
neon_store_reg32(s, dest, rd);
|
2019-06-13 20:56:21 +00:00
|
|
|
tcg_temp_free_i32(tcg_ctx, frn);
|
|
|
|
tcg_temp_free_i32(tcg_ctx, frm);
|
|
|
|
tcg_temp_free_i32(tcg_ctx, dest);
|
|
|
|
|
|
|
|
tcg_temp_free_i32(tcg_ctx, zero);
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
|
|
|
|
{
|
|
|
|
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
|
|
|
uint32_t rd, rn, rm;
|
|
|
|
bool dp = a->dp;
|
|
|
|
bool vmin = a->op;
|
|
|
|
TCGv_ptr fpst;
|
|
|
|
|
|
|
|
if (!dc_isar_feature(aa32_vminmaxnm, s)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* UNDEF accesses to D16-D31 if they don't exist */
|
|
|
|
if (dp && !dc_isar_feature(aa32_fp_d32, s) &&
|
|
|
|
((a->vm | a->vn | a->vd) & 0x10)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
rd = a->vd;
|
|
|
|
rn = a->vn;
|
|
|
|
rm = a->vm;
|
|
|
|
|
|
|
|
if (!vfp_access_check(s)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
fpst = get_fpstatus_ptr(s, 0);
|
|
|
|
|
|
|
|
if (dp) {
|
|
|
|
TCGv_i64 frn, frm, dest;
|
|
|
|
|
|
|
|
frn = tcg_temp_new_i64(tcg_ctx);
|
|
|
|
frm = tcg_temp_new_i64(tcg_ctx);
|
|
|
|
dest = tcg_temp_new_i64(tcg_ctx);
|
|
|
|
|
target/arm: Add helpers for VFP register loads and stores
The current VFP code has two different idioms for
loading and storing from the VFP register file:
1 using the gen_mov_F0_vreg() and similar functions,
which load and store to a fixed set of TCG globals
cpu_F0s, CPU_F0d, etc
2 by direct calls to tcg_gen_ld_f64() and friends
We want to phase out idiom 1 (because the use of the
fixed globals is a relic of a much older version of TCG),
but idiom 2 is quite longwinded:
tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg))
requires us to specify the 64-bitness twice, once in
the function name and once by passing 'true' to
vfp_reg_offset(). There's no guard against accidentally
passing the wrong flag.
Instead, let's move to a convention of accessing 64-bit
registers via the existing neon_load_reg64() and
neon_store_reg64(), and provide new neon_load_reg32()
and neon_store_reg32() for the 32-bit equivalents.
Implement the new functions and use them in the code in
translate-vfp.inc.c. We will convert the rest of the VFP
code as we do the decodetree conversion in subsequent
commits.
Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
|
|
|
neon_load_reg64(s, frn, rn);
|
|
|
|
neon_load_reg64(s, frm, rm);
|
2019-06-13 20:56:21 +00:00
|
|
|
if (vmin) {
|
|
|
|
gen_helper_vfp_minnumd(tcg_ctx, dest, frn, frm, fpst);
|
|
|
|
} else {
|
|
|
|
gen_helper_vfp_maxnumd(tcg_ctx, dest, frn, frm, fpst);
|
|
|
|
}
|
target/arm: Add helpers for VFP register loads and stores
The current VFP code has two different idioms for
loading and storing from the VFP register file:
1 using the gen_mov_F0_vreg() and similar functions,
which load and store to a fixed set of TCG globals
cpu_F0s, CPU_F0d, etc
2 by direct calls to tcg_gen_ld_f64() and friends
We want to phase out idiom 1 (because the use of the
fixed globals is a relic of a much older version of TCG),
but idiom 2 is quite longwinded:
tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg))
requires us to specify the 64-bitness twice, once in
the function name and once by passing 'true' to
vfp_reg_offset(). There's no guard against accidentally
passing the wrong flag.
Instead, let's move to a convention of accessing 64-bit
registers via the existing neon_load_reg64() and
neon_store_reg64(), and provide new neon_load_reg32()
and neon_store_reg32() for the 32-bit equivalents.
Implement the new functions and use them in the code in
translate-vfp.inc.c. We will convert the rest of the VFP
code as we do the decodetree conversion in subsequent
commits.
Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
|
|
|
neon_store_reg64(s, dest, rd);
|
2019-06-13 20:56:21 +00:00
|
|
|
tcg_temp_free_i64(tcg_ctx, frn);
|
|
|
|
tcg_temp_free_i64(tcg_ctx, frm);
|
|
|
|
tcg_temp_free_i64(tcg_ctx, dest);
|
|
|
|
} else {
|
|
|
|
TCGv_i32 frn, frm, dest;
|
|
|
|
|
|
|
|
frn = tcg_temp_new_i32(tcg_ctx);
|
|
|
|
frm = tcg_temp_new_i32(tcg_ctx);
|
|
|
|
dest = tcg_temp_new_i32(tcg_ctx);
|
|
|
|
|
target/arm: Add helpers for VFP register loads and stores
The current VFP code has two different idioms for
loading and storing from the VFP register file:
1 using the gen_mov_F0_vreg() and similar functions,
which load and store to a fixed set of TCG globals
cpu_F0s, CPU_F0d, etc
2 by direct calls to tcg_gen_ld_f64() and friends
We want to phase out idiom 1 (because the use of the
fixed globals is a relic of a much older version of TCG),
but idiom 2 is quite longwinded:
tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg))
requires us to specify the 64-bitness twice, once in
the function name and once by passing 'true' to
vfp_reg_offset(). There's no guard against accidentally
passing the wrong flag.
Instead, let's move to a convention of accessing 64-bit
registers via the existing neon_load_reg64() and
neon_store_reg64(), and provide new neon_load_reg32()
and neon_store_reg32() for the 32-bit equivalents.
Implement the new functions and use them in the code in
translate-vfp.inc.c. We will convert the rest of the VFP
code as we do the decodetree conversion in subsequent
commits.
Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
|
|
|
neon_load_reg32(s, frn, rn);
|
|
|
|
neon_load_reg32(s, frm, rm);
|
2019-06-13 20:56:21 +00:00
|
|
|
if (vmin) {
|
|
|
|
gen_helper_vfp_minnums(tcg_ctx, dest, frn, frm, fpst);
|
|
|
|
} else {
|
|
|
|
gen_helper_vfp_maxnums(tcg_ctx, dest, frn, frm, fpst);
|
|
|
|
}
|
target/arm: Add helpers for VFP register loads and stores
The current VFP code has two different idioms for
loading and storing from the VFP register file:
1 using the gen_mov_F0_vreg() and similar functions,
which load and store to a fixed set of TCG globals
cpu_F0s, CPU_F0d, etc
2 by direct calls to tcg_gen_ld_f64() and friends
We want to phase out idiom 1 (because the use of the
fixed globals is a relic of a much older version of TCG),
but idiom 2 is quite longwinded:
tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg))
requires us to specify the 64-bitness twice, once in
the function name and once by passing 'true' to
vfp_reg_offset(). There's no guard against accidentally
passing the wrong flag.
Instead, let's move to a convention of accessing 64-bit
registers via the existing neon_load_reg64() and
neon_store_reg64(), and provide new neon_load_reg32()
and neon_store_reg32() for the 32-bit equivalents.
Implement the new functions and use them in the code in
translate-vfp.inc.c. We will convert the rest of the VFP
code as we do the decodetree conversion in subsequent
commits.
Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
|
|
|
neon_store_reg32(s, dest, rd);
|
2019-06-13 20:56:21 +00:00
|
|
|
tcg_temp_free_i32(tcg_ctx, frn);
|
|
|
|
tcg_temp_free_i32(tcg_ctx, frm);
|
|
|
|
tcg_temp_free_i32(tcg_ctx, dest);
|
|
|
|
}
|
|
|
|
|
|
|
|
tcg_temp_free_ptr(tcg_ctx, fpst);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Table for converting the most common AArch32 encoding of
|
|
|
|
* rounding mode to arm_fprounding order (which matches the
|
|
|
|
* common AArch64 order); see ARM ARM pseudocode FPDecodeRM().
|
|
|
|
*/
|
|
|
|
static const uint8_t fp_decode_rm[] = {
|
|
|
|
FPROUNDING_TIEAWAY,
|
|
|
|
FPROUNDING_TIEEVEN,
|
|
|
|
FPROUNDING_POSINF,
|
|
|
|
FPROUNDING_NEGINF,
|
|
|
|
};
|
|
|
|
|
|
|
|
static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
|
|
|
|
{
|
|
|
|
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
|
|
|
uint32_t rd, rm;
|
|
|
|
bool dp = a->dp;
|
|
|
|
TCGv_ptr fpst;
|
|
|
|
TCGv_i32 tcg_rmode;
|
|
|
|
int rounding = fp_decode_rm[a->rm];
|
|
|
|
|
|
|
|
if (!dc_isar_feature(aa32_vrint, s)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* UNDEF accesses to D16-D31 if they don't exist */
|
|
|
|
if (dp && !dc_isar_feature(aa32_fp_d32, s) &&
|
|
|
|
((a->vm | a->vd) & 0x10)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
rd = a->vd;
|
|
|
|
rm = a->vm;
|
|
|
|
|
|
|
|
if (!vfp_access_check(s)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
fpst = get_fpstatus_ptr(s, 0);
|
|
|
|
|
|
|
|
tcg_rmode = tcg_const_i32(tcg_ctx, arm_rmode_to_sf(rounding));
|
|
|
|
gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, fpst);
|
|
|
|
|
|
|
|
if (dp) {
|
|
|
|
TCGv_i64 tcg_op;
|
|
|
|
TCGv_i64 tcg_res;
|
|
|
|
tcg_op = tcg_temp_new_i64(tcg_ctx);
|
|
|
|
tcg_res = tcg_temp_new_i64(tcg_ctx);
|
target/arm: Add helpers for VFP register loads and stores
The current VFP code has two different idioms for
loading and storing from the VFP register file:
1 using the gen_mov_F0_vreg() and similar functions,
which load and store to a fixed set of TCG globals
cpu_F0s, CPU_F0d, etc
2 by direct calls to tcg_gen_ld_f64() and friends
We want to phase out idiom 1 (because the use of the
fixed globals is a relic of a much older version of TCG),
but idiom 2 is quite longwinded:
tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg))
requires us to specify the 64-bitness twice, once in
the function name and once by passing 'true' to
vfp_reg_offset(). There's no guard against accidentally
passing the wrong flag.
Instead, let's move to a convention of accessing 64-bit
registers via the existing neon_load_reg64() and
neon_store_reg64(), and provide new neon_load_reg32()
and neon_store_reg32() for the 32-bit equivalents.
Implement the new functions and use them in the code in
translate-vfp.inc.c. We will convert the rest of the VFP
code as we do the decodetree conversion in subsequent
commits.
Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
|
|
|
neon_load_reg64(s, tcg_op, rm);
|
2019-06-13 20:56:21 +00:00
|
|
|
gen_helper_rintd(tcg_ctx, tcg_res, tcg_op, fpst);
|
target/arm: Add helpers for VFP register loads and stores
The current VFP code has two different idioms for
loading and storing from the VFP register file:
1 using the gen_mov_F0_vreg() and similar functions,
which load and store to a fixed set of TCG globals
cpu_F0s, CPU_F0d, etc
2 by direct calls to tcg_gen_ld_f64() and friends
We want to phase out idiom 1 (because the use of the
fixed globals is a relic of a much older version of TCG),
but idiom 2 is quite longwinded:
tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg))
requires us to specify the 64-bitness twice, once in
the function name and once by passing 'true' to
vfp_reg_offset(). There's no guard against accidentally
passing the wrong flag.
Instead, let's move to a convention of accessing 64-bit
registers via the existing neon_load_reg64() and
neon_store_reg64(), and provide new neon_load_reg32()
and neon_store_reg32() for the 32-bit equivalents.
Implement the new functions and use them in the code in
translate-vfp.inc.c. We will convert the rest of the VFP
code as we do the decodetree conversion in subsequent
commits.
Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
|
|
|
neon_store_reg64(s, tcg_res, rd);
|
2019-06-13 20:56:21 +00:00
|
|
|
tcg_temp_free_i64(tcg_ctx, tcg_op);
|
|
|
|
tcg_temp_free_i64(tcg_ctx, tcg_res);
|
|
|
|
} else {
|
|
|
|
TCGv_i32 tcg_op;
|
|
|
|
TCGv_i32 tcg_res;
|
|
|
|
tcg_op = tcg_temp_new_i32(tcg_ctx);
|
|
|
|
tcg_res = tcg_temp_new_i32(tcg_ctx);
|
target/arm: Add helpers for VFP register loads and stores
The current VFP code has two different idioms for
loading and storing from the VFP register file:
1 using the gen_mov_F0_vreg() and similar functions,
which load and store to a fixed set of TCG globals
cpu_F0s, CPU_F0d, etc
2 by direct calls to tcg_gen_ld_f64() and friends
We want to phase out idiom 1 (because the use of the
fixed globals is a relic of a much older version of TCG),
but idiom 2 is quite longwinded:
tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg))
requires us to specify the 64-bitness twice, once in
the function name and once by passing 'true' to
vfp_reg_offset(). There's no guard against accidentally
passing the wrong flag.
Instead, let's move to a convention of accessing 64-bit
registers via the existing neon_load_reg64() and
neon_store_reg64(), and provide new neon_load_reg32()
and neon_store_reg32() for the 32-bit equivalents.
Implement the new functions and use them in the code in
translate-vfp.inc.c. We will convert the rest of the VFP
code as we do the decodetree conversion in subsequent
commits.
Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
|
|
|
neon_load_reg32(s, tcg_op, rm);
|
2019-06-13 20:56:21 +00:00
|
|
|
gen_helper_rints(tcg_ctx, tcg_res, tcg_op, fpst);
|
target/arm: Add helpers for VFP register loads and stores
The current VFP code has two different idioms for
loading and storing from the VFP register file:
1 using the gen_mov_F0_vreg() and similar functions,
which load and store to a fixed set of TCG globals
cpu_F0s, CPU_F0d, etc
2 by direct calls to tcg_gen_ld_f64() and friends
We want to phase out idiom 1 (because the use of the
fixed globals is a relic of a much older version of TCG),
but idiom 2 is quite longwinded:
tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg))
requires us to specify the 64-bitness twice, once in
the function name and once by passing 'true' to
vfp_reg_offset(). There's no guard against accidentally
passing the wrong flag.
Instead, let's move to a convention of accessing 64-bit
registers via the existing neon_load_reg64() and
neon_store_reg64(), and provide new neon_load_reg32()
and neon_store_reg32() for the 32-bit equivalents.
Implement the new functions and use them in the code in
translate-vfp.inc.c. We will convert the rest of the VFP
code as we do the decodetree conversion in subsequent
commits.
Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
|
|
|
neon_store_reg32(s, tcg_res, rd);
|
2019-06-13 20:56:21 +00:00
|
|
|
tcg_temp_free_i32(tcg_ctx, tcg_op);
|
|
|
|
tcg_temp_free_i32(tcg_ctx, tcg_res);
|
|
|
|
}
|
|
|
|
|
|
|
|
gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, fpst);
|
|
|
|
tcg_temp_free_i32(tcg_ctx, tcg_rmode);
|
|
|
|
|
|
|
|
tcg_temp_free_ptr(tcg_ctx, fpst);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
|
|
|
|
{
|
|
|
|
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
|
|
|
uint32_t rd, rm;
|
|
|
|
bool dp = a->dp;
|
|
|
|
TCGv_ptr fpst;
|
|
|
|
TCGv_i32 tcg_rmode, tcg_shift;
|
|
|
|
int rounding = fp_decode_rm[a->rm];
|
|
|
|
bool is_signed = a->op;
|
|
|
|
|
|
|
|
if (!dc_isar_feature(aa32_vcvt_dr, s)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* UNDEF accesses to D16-D31 if they don't exist */
|
|
|
|
if (dp && !dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
rd = a->vd;
|
|
|
|
rm = a->vm;
|
|
|
|
|
|
|
|
if (!vfp_access_check(s)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
fpst = get_fpstatus_ptr(s, 0);
|
|
|
|
|
|
|
|
tcg_shift = tcg_const_i32(tcg_ctx, 0);
|
|
|
|
|
|
|
|
tcg_rmode = tcg_const_i32(tcg_ctx, arm_rmode_to_sf(rounding));
|
|
|
|
gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, fpst);
|
|
|
|
|
|
|
|
if (dp) {
|
|
|
|
TCGv_i64 tcg_double, tcg_res;
|
|
|
|
TCGv_i32 tcg_tmp;
|
|
|
|
tcg_double = tcg_temp_new_i64(tcg_ctx);
|
|
|
|
tcg_res = tcg_temp_new_i64(tcg_ctx);
|
|
|
|
tcg_tmp = tcg_temp_new_i32(tcg_ctx);
|
target/arm: Add helpers for VFP register loads and stores
The current VFP code has two different idioms for
loading and storing from the VFP register file:
1 using the gen_mov_F0_vreg() and similar functions,
which load and store to a fixed set of TCG globals
cpu_F0s, CPU_F0d, etc
2 by direct calls to tcg_gen_ld_f64() and friends
We want to phase out idiom 1 (because the use of the
fixed globals is a relic of a much older version of TCG),
but idiom 2 is quite longwinded:
tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg))
requires us to specify the 64-bitness twice, once in
the function name and once by passing 'true' to
vfp_reg_offset(). There's no guard against accidentally
passing the wrong flag.
Instead, let's move to a convention of accessing 64-bit
registers via the existing neon_load_reg64() and
neon_store_reg64(), and provide new neon_load_reg32()
and neon_store_reg32() for the 32-bit equivalents.
Implement the new functions and use them in the code in
translate-vfp.inc.c. We will convert the rest of the VFP
code as we do the decodetree conversion in subsequent
commits.
Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
|
|
|
neon_load_reg64(s, tcg_double, rm);
|
2019-06-13 20:56:21 +00:00
|
|
|
if (is_signed) {
|
|
|
|
gen_helper_vfp_tosld(tcg_ctx, tcg_res, tcg_double, tcg_shift, fpst);
|
|
|
|
} else {
|
|
|
|
gen_helper_vfp_tould(tcg_ctx, tcg_res, tcg_double, tcg_shift, fpst);
|
|
|
|
}
|
|
|
|
tcg_gen_extrl_i64_i32(tcg_ctx, tcg_tmp, tcg_res);
|
target/arm: Add helpers for VFP register loads and stores
The current VFP code has two different idioms for
loading and storing from the VFP register file:
1 using the gen_mov_F0_vreg() and similar functions,
which load and store to a fixed set of TCG globals
cpu_F0s, CPU_F0d, etc
2 by direct calls to tcg_gen_ld_f64() and friends
We want to phase out idiom 1 (because the use of the
fixed globals is a relic of a much older version of TCG),
but idiom 2 is quite longwinded:
tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg))
requires us to specify the 64-bitness twice, once in
the function name and once by passing 'true' to
vfp_reg_offset(). There's no guard against accidentally
passing the wrong flag.
Instead, let's move to a convention of accessing 64-bit
registers via the existing neon_load_reg64() and
neon_store_reg64(), and provide new neon_load_reg32()
and neon_store_reg32() for the 32-bit equivalents.
Implement the new functions and use them in the code in
translate-vfp.inc.c. We will convert the rest of the VFP
code as we do the decodetree conversion in subsequent
commits.
Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
|
|
|
neon_store_reg32(s, tcg_tmp, rd);
|
2019-06-13 20:56:21 +00:00
|
|
|
tcg_temp_free_i32(tcg_ctx, tcg_tmp);
|
|
|
|
tcg_temp_free_i64(tcg_ctx, tcg_res);
|
|
|
|
tcg_temp_free_i64(tcg_ctx, tcg_double);
|
|
|
|
} else {
|
|
|
|
TCGv_i32 tcg_single, tcg_res;
|
|
|
|
tcg_single = tcg_temp_new_i32(tcg_ctx);
|
|
|
|
tcg_res = tcg_temp_new_i32(tcg_ctx);
|
target/arm: Add helpers for VFP register loads and stores
The current VFP code has two different idioms for
loading and storing from the VFP register file:
1 using the gen_mov_F0_vreg() and similar functions,
which load and store to a fixed set of TCG globals
cpu_F0s, CPU_F0d, etc
2 by direct calls to tcg_gen_ld_f64() and friends
We want to phase out idiom 1 (because the use of the
fixed globals is a relic of a much older version of TCG),
but idiom 2 is quite longwinded:
tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg))
requires us to specify the 64-bitness twice, once in
the function name and once by passing 'true' to
vfp_reg_offset(). There's no guard against accidentally
passing the wrong flag.
Instead, let's move to a convention of accessing 64-bit
registers via the existing neon_load_reg64() and
neon_store_reg64(), and provide new neon_load_reg32()
and neon_store_reg32() for the 32-bit equivalents.
Implement the new functions and use them in the code in
translate-vfp.inc.c. We will convert the rest of the VFP
code as we do the decodetree conversion in subsequent
commits.
Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
|
|
|
neon_load_reg32(s, tcg_single, rm);
|
2019-06-13 20:56:21 +00:00
|
|
|
if (is_signed) {
|
|
|
|
gen_helper_vfp_tosls(tcg_ctx, tcg_res, tcg_single, tcg_shift, fpst);
|
|
|
|
} else {
|
|
|
|
gen_helper_vfp_touls(tcg_ctx, tcg_res, tcg_single, tcg_shift, fpst);
|
|
|
|
}
|
target/arm: Add helpers for VFP register loads and stores
The current VFP code has two different idioms for
loading and storing from the VFP register file:
1 using the gen_mov_F0_vreg() and similar functions,
which load and store to a fixed set of TCG globals
cpu_F0s, CPU_F0d, etc
2 by direct calls to tcg_gen_ld_f64() and friends
We want to phase out idiom 1 (because the use of the
fixed globals is a relic of a much older version of TCG),
but idiom 2 is quite longwinded:
tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg))
requires us to specify the 64-bitness twice, once in
the function name and once by passing 'true' to
vfp_reg_offset(). There's no guard against accidentally
passing the wrong flag.
Instead, let's move to a convention of accessing 64-bit
registers via the existing neon_load_reg64() and
neon_store_reg64(), and provide new neon_load_reg32()
and neon_store_reg32() for the 32-bit equivalents.
Implement the new functions and use them in the code in
translate-vfp.inc.c. We will convert the rest of the VFP
code as we do the decodetree conversion in subsequent
commits.
Backports commit 160f3b64c5cc4c8a09a1859edc764882ce6ad6bf from qemu
2019-06-13 21:01:57 +00:00
|
|
|
neon_store_reg32(s, tcg_res, rd);
|
2019-06-13 20:56:21 +00:00
|
|
|
tcg_temp_free_i32(tcg_ctx, tcg_res);
|
|
|
|
tcg_temp_free_i32(tcg_ctx, tcg_single);
|
|
|
|
}
|
|
|
|
|
|
|
|
gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, fpst);
|
|
|
|
tcg_temp_free_i32(tcg_ctx, tcg_rmode);
|
|
|
|
|
|
|
|
tcg_temp_free_i32(tcg_ctx, tcg_shift);
|
|
|
|
|
|
|
|
tcg_temp_free_ptr(tcg_ctx, fpst);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
2019-06-13 21:09:09 +00:00
|
|
|
|
|
|
|
static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
|
|
|
|
{
|
|
|
|
/* VMOV scalar to general purpose register */
|
|
|
|
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
|
|
|
TCGv_i32 tmp;
|
|
|
|
int pass;
|
|
|
|
uint32_t offset;
|
|
|
|
|
|
|
|
/* UNDEF accesses to D16-D31 if they don't exist */
|
|
|
|
if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
offset = a->index << a->size;
|
|
|
|
pass = extract32(offset, 2, 1);
|
|
|
|
offset = extract32(offset, 0, 2) * 8;
|
|
|
|
|
|
|
|
if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!vfp_access_check(s)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
tmp = neon_load_reg(s, a->vn, pass);
|
|
|
|
switch (a->size) {
|
|
|
|
case 0:
|
|
|
|
if (offset) {
|
|
|
|
tcg_gen_shri_i32(tcg_ctx, tmp, tmp, offset);
|
|
|
|
}
|
|
|
|
if (a->u) {
|
|
|
|
gen_uxtb(tmp);
|
|
|
|
} else {
|
|
|
|
gen_sxtb(tmp);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
if (a->u) {
|
|
|
|
if (offset) {
|
|
|
|
tcg_gen_shri_i32(tcg_ctx, tmp, tmp, 16);
|
|
|
|
} else {
|
|
|
|
gen_uxth(tmp);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (offset) {
|
|
|
|
tcg_gen_sari_i32(tcg_ctx, tmp, tmp, 16);
|
|
|
|
} else {
|
|
|
|
gen_sxth(tmp);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
store_reg(s, a->rt, tmp);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
|
|
|
|
{
|
|
|
|
/* VMOV general purpose register to scalar */
|
|
|
|
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
|
|
|
TCGv_i32 tmp, tmp2;
|
|
|
|
int pass;
|
|
|
|
uint32_t offset;
|
|
|
|
|
|
|
|
/* UNDEF accesses to D16-D31 if they don't exist */
|
|
|
|
if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
offset = a->index << a->size;
|
|
|
|
pass = extract32(offset, 2, 1);
|
|
|
|
offset = extract32(offset, 0, 2) * 8;
|
|
|
|
|
|
|
|
if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!vfp_access_check(s)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
tmp = load_reg(s, a->rt);
|
|
|
|
switch (a->size) {
|
|
|
|
case 0:
|
|
|
|
tmp2 = neon_load_reg(s, a->vn, pass);
|
|
|
|
tcg_gen_deposit_i32(tcg_ctx, tmp, tmp2, tmp, offset, 8);
|
|
|
|
tcg_temp_free_i32(tcg_ctx, tmp2);
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
tmp2 = neon_load_reg(s, a->vn, pass);
|
|
|
|
tcg_gen_deposit_i32(tcg_ctx, tmp, tmp2, tmp, offset, 16);
|
|
|
|
tcg_temp_free_i32(tcg_ctx, tmp2);
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
neon_store_reg(s, a->vn, pass, tmp);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
|
|
|
|
{
|
|
|
|
/* VDUP (general purpose register) */
|
|
|
|
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
|
|
|
TCGv_i32 tmp;
|
|
|
|
int size, vec_size;
|
|
|
|
|
|
|
|
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* UNDEF accesses to D16-D31 if they don't exist */
|
|
|
|
if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (a->b && a->e) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (a->q && (a->vn & 1)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
vec_size = a->q ? 16 : 8;
|
|
|
|
if (a->b) {
|
|
|
|
size = 0;
|
|
|
|
} else if (a->e) {
|
|
|
|
size = 1;
|
|
|
|
} else {
|
|
|
|
size = 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!vfp_access_check(s)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
tmp = load_reg(s, a->rt);
|
|
|
|
tcg_gen_gvec_dup_i32(tcg_ctx, size, neon_reg_offset(a->vn, 0),
|
|
|
|
vec_size, vec_size, tmp);
|
|
|
|
tcg_temp_free_i32(tcg_ctx, tmp);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
2019-06-13 21:16:35 +00:00
|
|
|
|
|
|
|
static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
|
|
|
|
{
|
|
|
|
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
|
|
|
TCGv_i32 tmp;
|
|
|
|
bool ignore_vfp_enabled = false;
|
|
|
|
|
|
|
|
if (arm_dc_feature(s, ARM_FEATURE_M)) {
|
|
|
|
/*
|
|
|
|
* The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
|
|
|
|
* Writes to R15 are UNPREDICTABLE; we choose to undef.
|
|
|
|
*/
|
|
|
|
if (a->rt == 15 || a->reg != ARM_VFP_FPSCR) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (a->reg) {
|
|
|
|
case ARM_VFP_FPSID:
|
|
|
|
/*
|
|
|
|
* VFPv2 allows access to FPSID from userspace; VFPv3 restricts
|
|
|
|
* all ID registers to privileged access only.
|
|
|
|
*/
|
|
|
|
if (IS_USER(s) && arm_dc_feature(s, ARM_FEATURE_VFP3)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
ignore_vfp_enabled = true;
|
|
|
|
break;
|
|
|
|
case ARM_VFP_MVFR0:
|
|
|
|
case ARM_VFP_MVFR1:
|
|
|
|
if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_MVFR)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
ignore_vfp_enabled = true;
|
|
|
|
break;
|
|
|
|
case ARM_VFP_MVFR2:
|
|
|
|
if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_V8)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
ignore_vfp_enabled = true;
|
|
|
|
break;
|
|
|
|
case ARM_VFP_FPSCR:
|
|
|
|
break;
|
|
|
|
case ARM_VFP_FPEXC:
|
|
|
|
if (IS_USER(s)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
ignore_vfp_enabled = true;
|
|
|
|
break;
|
|
|
|
case ARM_VFP_FPINST:
|
|
|
|
case ARM_VFP_FPINST2:
|
|
|
|
/* Not present in VFPv3 */
|
|
|
|
if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_VFP3)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!full_vfp_access_check(s, ignore_vfp_enabled)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (a->l) {
|
|
|
|
/* VMRS, move VFP special register to gp register */
|
|
|
|
switch (a->reg) {
|
|
|
|
case ARM_VFP_FPSID:
|
|
|
|
case ARM_VFP_FPEXC:
|
|
|
|
case ARM_VFP_FPINST:
|
|
|
|
case ARM_VFP_FPINST2:
|
|
|
|
case ARM_VFP_MVFR0:
|
|
|
|
case ARM_VFP_MVFR1:
|
|
|
|
case ARM_VFP_MVFR2:
|
|
|
|
tmp = load_cpu_field(s, vfp.xregs[a->reg]);
|
|
|
|
break;
|
|
|
|
case ARM_VFP_FPSCR:
|
|
|
|
if (a->rt == 15) {
|
|
|
|
tmp = load_cpu_field(s, vfp.xregs[ARM_VFP_FPSCR]);
|
|
|
|
tcg_gen_andi_i32(tcg_ctx, tmp, tmp, 0xf0000000);
|
|
|
|
} else {
|
|
|
|
tmp = tcg_temp_new_i32(tcg_ctx);
|
|
|
|
gen_helper_vfp_get_fpscr(tcg_ctx, tmp, tcg_ctx->cpu_env);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
|
|
|
|
if (a->rt == 15) {
|
|
|
|
/* Set the 4 flag bits in the CPSR. */
|
|
|
|
gen_set_nzcv(s, tmp);
|
|
|
|
tcg_temp_free_i32(tcg_ctx, tmp);
|
|
|
|
} else {
|
|
|
|
store_reg(s, a->rt, tmp);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* VMSR, move gp register to VFP special register */
|
|
|
|
switch (a->reg) {
|
|
|
|
case ARM_VFP_FPSID:
|
|
|
|
case ARM_VFP_MVFR0:
|
|
|
|
case ARM_VFP_MVFR1:
|
|
|
|
case ARM_VFP_MVFR2:
|
|
|
|
/* Writes are ignored. */
|
|
|
|
break;
|
|
|
|
case ARM_VFP_FPSCR:
|
|
|
|
tmp = load_reg(s, a->rt);
|
|
|
|
gen_helper_vfp_set_fpscr(tcg_ctx, tcg_ctx->cpu_env, tmp);
|
|
|
|
tcg_temp_free_i32(tcg_ctx, tmp);
|
|
|
|
gen_lookup_tb(s);
|
|
|
|
break;
|
|
|
|
case ARM_VFP_FPEXC:
|
|
|
|
/*
|
|
|
|
* TODO: VFP subarchitecture support.
|
|
|
|
* For now, keep the EN bit only
|
|
|
|
*/
|
|
|
|
tmp = load_reg(s, a->rt);
|
|
|
|
tcg_gen_andi_i32(tcg_ctx, tmp, tmp, 1 << 30);
|
|
|
|
store_cpu_field(s, tmp, vfp.xregs[a->reg]);
|
|
|
|
gen_lookup_tb(s);
|
|
|
|
break;
|
|
|
|
case ARM_VFP_FPINST:
|
|
|
|
case ARM_VFP_FPINST2:
|
|
|
|
tmp = load_reg(s, a->rt);
|
|
|
|
store_cpu_field(s, tmp, vfp.xregs[a->reg]);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
|
|
|
|
{
|
|
|
|
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
|
|
|
TCGv_i32 tmp;
|
|
|
|
|
|
|
|
if (!vfp_access_check(s)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (a->l) {
|
|
|
|
/* VFP to general purpose register */
|
|
|
|
tmp = tcg_temp_new_i32(tcg_ctx);
|
|
|
|
neon_load_reg32(s, tmp, a->vn);
|
|
|
|
if (a->rt == 15) {
|
|
|
|
/* Set the 4 flag bits in the CPSR. */
|
|
|
|
gen_set_nzcv(s, tmp);
|
|
|
|
tcg_temp_free_i32(tcg_ctx, tmp);
|
|
|
|
} else {
|
|
|
|
store_reg(s, a->rt, tmp);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* general purpose register to VFP */
|
|
|
|
tmp = load_reg(s, a->rt);
|
|
|
|
neon_store_reg32(s, tmp, a->vn);
|
|
|
|
tcg_temp_free_i32(tcg_ctx, tmp);
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
2019-06-13 21:19:58 +00:00
|
|
|
|
|
|
|
static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a)
|
|
|
|
{
|
|
|
|
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
|
|
|
TCGv_i32 tmp;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* VMOV between two general-purpose registers and two single precision
|
|
|
|
* floating point registers
|
|
|
|
*/
|
|
|
|
if (!vfp_access_check(s)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (a->op) {
|
|
|
|
/* fpreg to gpreg */
|
|
|
|
tmp = tcg_temp_new_i32(tcg_ctx);
|
|
|
|
neon_load_reg32(s, tmp, a->vm);
|
|
|
|
store_reg(s, a->rt, tmp);
|
|
|
|
tmp = tcg_temp_new_i32(tcg_ctx);
|
|
|
|
neon_load_reg32(s, tmp, a->vm + 1);
|
|
|
|
store_reg(s, a->rt2, tmp);
|
|
|
|
} else {
|
|
|
|
/* gpreg to fpreg */
|
|
|
|
tmp = load_reg(s, a->rt);
|
|
|
|
neon_store_reg32(s, tmp, a->vm);
|
|
|
|
tmp = load_reg(s, a->rt2);
|
|
|
|
neon_store_reg32(s, tmp, a->vm + 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_sp *a)
|
|
|
|
{
|
|
|
|
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
|
|
|
TCGv_i32 tmp;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* VMOV between two general-purpose registers and one double precision
|
|
|
|
* floating point register
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* UNDEF accesses to D16-D31 if they don't exist */
|
|
|
|
if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!vfp_access_check(s)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (a->op) {
|
|
|
|
/* fpreg to gpreg */
|
|
|
|
tmp = tcg_temp_new_i32(tcg_ctx);
|
|
|
|
neon_load_reg32(s, tmp, a->vm * 2);
|
|
|
|
store_reg(s, a->rt, tmp);
|
|
|
|
tmp = tcg_temp_new_i32(tcg_ctx);
|
|
|
|
neon_load_reg32(s, tmp, a->vm * 2 + 1);
|
|
|
|
store_reg(s, a->rt2, tmp);
|
|
|
|
} else {
|
|
|
|
/* gpreg to fpreg */
|
|
|
|
tmp = load_reg(s, a->rt);
|
|
|
|
neon_store_reg32(s, tmp, a->vm * 2);
|
|
|
|
tcg_temp_free_i32(tcg_ctx, tmp);
|
|
|
|
tmp = load_reg(s, a->rt2);
|
|
|
|
neon_store_reg32(s, tmp, a->vm * 2 + 1);
|
|
|
|
tcg_temp_free_i32(tcg_ctx, tmp);
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
2019-06-13 21:22:47 +00:00
|
|
|
|
|
|
|
static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
|
|
|
|
{
|
|
|
|
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
|
|
|
uint32_t offset;
|
|
|
|
TCGv_i32 addr;
|
|
|
|
|
|
|
|
if (!vfp_access_check(s)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
offset = a->imm << 2;
|
|
|
|
if (!a->u) {
|
|
|
|
offset = -offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (s->thumb && a->rn == 15) {
|
|
|
|
/* This is actually UNPREDICTABLE */
|
|
|
|
addr = tcg_temp_new_i32(tcg_ctx);
|
|
|
|
tcg_gen_movi_i32(tcg_ctx, addr, s->pc & ~2);
|
|
|
|
} else {
|
|
|
|
addr = load_reg(s, a->rn);
|
|
|
|
}
|
|
|
|
tcg_gen_addi_i32(tcg_ctx, addr, addr, offset);
|
|
|
|
if (a->l) {
|
|
|
|
gen_vfp_ld(s, false, addr);
|
|
|
|
gen_mov_vreg_F0(s, false, a->vd);
|
|
|
|
} else {
|
|
|
|
gen_mov_F0_vreg(s, false, a->vd);
|
|
|
|
gen_vfp_st(s, false, addr);
|
|
|
|
}
|
|
|
|
tcg_temp_free_i32(tcg_ctx, addr);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_sp *a)
|
|
|
|
{
|
|
|
|
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
|
|
|
uint32_t offset;
|
|
|
|
TCGv_i32 addr;
|
|
|
|
|
|
|
|
/* UNDEF accesses to D16-D31 if they don't exist */
|
|
|
|
if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!vfp_access_check(s)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
offset = a->imm << 2;
|
|
|
|
if (!a->u) {
|
|
|
|
offset = -offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (s->thumb && a->rn == 15) {
|
|
|
|
/* This is actually UNPREDICTABLE */
|
|
|
|
addr = tcg_temp_new_i32(tcg_ctx);
|
|
|
|
tcg_gen_movi_i32(tcg_ctx, addr, s->pc & ~2);
|
|
|
|
} else {
|
|
|
|
addr = load_reg(s, a->rn);
|
|
|
|
}
|
|
|
|
tcg_gen_addi_i32(tcg_ctx, addr, addr, offset);
|
|
|
|
if (a->l) {
|
|
|
|
gen_vfp_ld(s, true, addr);
|
|
|
|
gen_mov_vreg_F0(s, true, a->vd);
|
|
|
|
} else {
|
|
|
|
gen_mov_F0_vreg(s, true, a->vd);
|
|
|
|
gen_vfp_st(s, true, addr);
|
|
|
|
}
|
|
|
|
tcg_temp_free_i32(tcg_ctx, addr);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
2019-06-13 21:25:34 +00:00
|
|
|
|
|
|
|
static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
|
|
|
|
{
|
|
|
|
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
|
|
|
uint32_t offset;
|
|
|
|
TCGv_i32 addr;
|
|
|
|
int i, n;
|
|
|
|
|
|
|
|
n = a->imm;
|
|
|
|
|
|
|
|
if (n == 0 || (a->vd + n) > 32) {
|
|
|
|
/*
|
|
|
|
* UNPREDICTABLE cases for bad immediates: we choose to
|
|
|
|
* UNDEF to avoid generating huge numbers of TCG ops
|
|
|
|
*/
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
if (a->rn == 15 && a->w) {
|
|
|
|
/* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!vfp_access_check(s)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (s->thumb && a->rn == 15) {
|
|
|
|
/* This is actually UNPREDICTABLE */
|
|
|
|
addr = tcg_temp_new_i32(tcg_ctx);
|
|
|
|
tcg_gen_movi_i32(tcg_ctx, addr, s->pc & ~2);
|
|
|
|
} else {
|
|
|
|
addr = load_reg(s, a->rn);
|
|
|
|
}
|
|
|
|
if (a->p) {
|
|
|
|
/* pre-decrement */
|
|
|
|
tcg_gen_addi_i32(tcg_ctx, addr, addr, -(a->imm << 2));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (s->v8m_stackcheck && a->rn == 13 && a->w) {
|
|
|
|
/*
|
|
|
|
* Here 'addr' is the lowest address we will store to,
|
|
|
|
* and is either the old SP (if post-increment) or
|
|
|
|
* the new SP (if pre-decrement). For post-increment
|
|
|
|
* where the old value is below the limit and the new
|
|
|
|
* value is above, it is UNKNOWN whether the limit check
|
|
|
|
* triggers; we choose to trigger.
|
|
|
|
*/
|
|
|
|
gen_helper_v8m_stackcheck(tcg_ctx, tcg_ctx->cpu_env, addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
offset = 4;
|
|
|
|
for (i = 0; i < n; i++) {
|
|
|
|
if (a->l) {
|
|
|
|
/* load */
|
|
|
|
gen_vfp_ld(s, false, addr);
|
|
|
|
gen_mov_vreg_F0(s, false, a->vd + i);
|
|
|
|
} else {
|
|
|
|
/* store */
|
|
|
|
gen_mov_F0_vreg(s, false, a->vd + i);
|
|
|
|
gen_vfp_st(s, false, addr);
|
|
|
|
}
|
|
|
|
tcg_gen_addi_i32(tcg_ctx, addr, addr, offset);
|
|
|
|
}
|
|
|
|
if (a->w) {
|
|
|
|
/* writeback */
|
|
|
|
if (a->p) {
|
|
|
|
offset = -offset * n;
|
|
|
|
tcg_gen_addi_i32(tcg_ctx, addr, addr, offset);
|
|
|
|
}
|
|
|
|
store_reg(s, a->rn, addr);
|
|
|
|
} else {
|
|
|
|
tcg_temp_free_i32(tcg_ctx, addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
|
|
|
|
{
|
|
|
|
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
|
|
|
uint32_t offset;
|
|
|
|
TCGv_i32 addr;
|
|
|
|
int i, n;
|
|
|
|
|
|
|
|
n = a->imm >> 1;
|
|
|
|
|
|
|
|
if (n == 0 || (a->vd + n) > 32 || n > 16) {
|
|
|
|
/*
|
|
|
|
* UNPREDICTABLE cases for bad immediates: we choose to
|
|
|
|
* UNDEF to avoid generating huge numbers of TCG ops
|
|
|
|
*/
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
if (a->rn == 15 && a->w) {
|
|
|
|
/* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* UNDEF accesses to D16-D31 if they don't exist */
|
|
|
|
if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd + n) > 16) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!vfp_access_check(s)) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (s->thumb && a->rn == 15) {
|
|
|
|
/* This is actually UNPREDICTABLE */
|
|
|
|
addr = tcg_temp_new_i32(tcg_ctx);
|
|
|
|
tcg_gen_movi_i32(tcg_ctx, addr, s->pc & ~2);
|
|
|
|
} else {
|
|
|
|
addr = load_reg(s, a->rn);
|
|
|
|
}
|
|
|
|
if (a->p) {
|
|
|
|
/* pre-decrement */
|
|
|
|
tcg_gen_addi_i32(tcg_ctx, addr, addr, -(a->imm << 2));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (s->v8m_stackcheck && a->rn == 13 && a->w) {
|
|
|
|
/*
|
|
|
|
* Here 'addr' is the lowest address we will store to,
|
|
|
|
* and is either the old SP (if post-increment) or
|
|
|
|
* the new SP (if pre-decrement). For post-increment
|
|
|
|
* where the old value is below the limit and the new
|
|
|
|
* value is above, it is UNKNOWN whether the limit check
|
|
|
|
* triggers; we choose to trigger.
|
|
|
|
*/
|
|
|
|
gen_helper_v8m_stackcheck(tcg_ctx, tcg_ctx->cpu_env, addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
offset = 8;
|
|
|
|
for (i = 0; i < n; i++) {
|
|
|
|
if (a->l) {
|
|
|
|
/* load */
|
|
|
|
gen_vfp_ld(s, true, addr);
|
|
|
|
gen_mov_vreg_F0(s, true, a->vd + i);
|
|
|
|
} else {
|
|
|
|
/* store */
|
|
|
|
gen_mov_F0_vreg(s, true, a->vd + i);
|
|
|
|
gen_vfp_st(s, true, addr);
|
|
|
|
}
|
|
|
|
tcg_gen_addi_i32(tcg_ctx, addr, addr, offset);
|
|
|
|
}
|
|
|
|
if (a->w) {
|
|
|
|
/* writeback */
|
|
|
|
if (a->p) {
|
|
|
|
offset = -offset * n;
|
|
|
|
} else if (a->imm & 1) {
|
|
|
|
offset = 4;
|
|
|
|
} else {
|
|
|
|
offset = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (offset != 0) {
|
|
|
|
tcg_gen_addi_i32(tcg_ctx, addr, addr, offset);
|
|
|
|
}
|
|
|
|
store_reg(s, a->rn, addr);
|
|
|
|
} else {
|
|
|
|
tcg_temp_free_i32(tcg_ctx, addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|