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target-mips: check CP0 enabled for CACHE instruction also in R6

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Backports commit 40d48212f934d4deab40ffe84a0f9c4c553d4742 from qemu
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Leon Alrae 2018-02-22 10:47:52 -05:00 committed by Lioncash
parent 70306ec586
commit 0c5ebbd096
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qemu/target-mips/translate.c
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@ -17322,6 +17322,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
/* Treat as NOP. */
break;
case R6_OPC_CACHE:
check_cp0_enabled(ctx);
/* Treat as NOP. */
break;
case R6_OPC_SC: