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target-arm: Report S/NS status in the CPU debug logs

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If this CPU supports EL3, enhance the printing of the current
CPU mode in debug logging to distinguish S from NS modes as
appropriate.

Backports commit 06e5cf7acd1f94ab7c1cd6945974a1f039672940 from qemu
This commit is contained in:
Peter Maydell 2018-02-17 14:51:26 -05:00 committed by Lioncash
parent 78d26764b7
commit 0ed5787f89
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 20 additions and 3 deletions
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11
qemu/target-arm/translate-a64.c
View file

@ -140,6 +140,7 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
uint32_t psr = pstate_read(env); uint32_t psr = pstate_read(env);
int i; int i;
int el = arm_current_el(env); int el = arm_current_el(env);
const char *ns_status;
cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n",
env->pc, env->xregs[31]); env->pc, env->xregs[31]);
@ -151,12 +152,20 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
cpu_fprintf(f, " "); cpu_fprintf(f, " ");
} }
} }
cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c EL%d%c\n",
if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
} else {
ns_status = "";
}
cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
psr, psr,
psr & PSTATE_N ? 'N' : '-', psr & PSTATE_N ? 'N' : '-',
psr & PSTATE_Z ? 'Z' : '-', psr & PSTATE_Z ? 'Z' : '-',
psr & PSTATE_C ? 'C' : '-', psr & PSTATE_C ? 'C' : '-',
psr & PSTATE_V ? 'V' : '-', psr & PSTATE_V ? 'V' : '-',
ns_status,
el, el,
psr & PSTATE_SP ? 'h' : 't'); psr & PSTATE_SP ? 'h' : 't');

12
qemu/target-arm/translate.c
View file

@ -11803,6 +11803,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
ARMCPU *cpu = ARM_CPU(cs); ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env; CPUARMState *env = &cpu->env;
int i; int i;
const char *ns_status;
if (is_a64(env)) { if (is_a64(env)) {
aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags); aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags);
@ -11817,10 +11818,16 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
cpu_fprintf(f, " "); cpu_fprintf(f, " ");
} }
if (arm_feature(env, ARM_FEATURE_EL3) &&
(psr & CPSR_M) != ARM_CPU_MODE_MON) {
ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
} else {
ns_status = "";
}
if (arm_feature(env, ARM_FEATURE_M)) { if (arm_feature(env, ARM_FEATURE_M)) {
uint32_t xpsr = xpsr_read(env); uint32_t xpsr = xpsr_read(env);
const char *mode; const char *mode;
const char *ns_status = "";
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
ns_status = env->v7m.secure ? "S " : "NS "; ns_status = env->v7m.secure ? "S " : "NS ";
@ -11854,13 +11861,14 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
} }
cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n", cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
psr, psr,
psr & (1 << 31) ? 'N' : '-', psr & (1 << 31) ? 'N' : '-',
psr & (1 << 30) ? 'Z' : '-', psr & (1 << 30) ? 'Z' : '-',
psr & (1 << 29) ? 'C' : '-', psr & (1 << 29) ? 'C' : '-',
psr & (1 << 28) ? 'V' : '-', psr & (1 << 28) ? 'V' : '-',
psr & CPSR_T ? 'T' : 'A', psr & CPSR_T ? 'T' : 'A',
ns_status,
cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
} }