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target/arm: Register second AddressSpace for secure v8M CPUs

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If a v8M CPU supports the security extension then we need to
give it two AddressSpaces, the same way we do already for
an A profile core with EL3.

Backports commit 1d2091bc75ab7f9e2c43082f361a528a63c79527 from qemu
This commit is contained in:
Peter Maydell 2018-03-04 20:50:58 -05:00 committed by Lioncash
parent 8ce42ad30c
commit 13bad2c234
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 5 additions and 7 deletions
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12
qemu/target/arm/cpu.c
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@ -631,15 +631,11 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
arm_cpu_register_gdb_regs_for_features(cpu);
#ifndef CONFIG_USER_ONLY
if (cpu->has_el3) {
cs->num_ases = 2;
} else {
cs->num_ases = 1;
}
if (cpu->has_el3) {
if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {
AddressSpace *as;
cs->num_ases = 2;
if (!cpu->secure_memory) {
cpu->secure_memory = cs->memory;
}
@ -647,6 +643,8 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
cpu->secure_memory,
"cpu-secure-memory");
cpu_address_space_init(cs, as, ARMASIdx_S);
} else {
cs->num_ases = 1;
}
cpu_address_space_init(cs,
address_space_init_shareable(uc,