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target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers

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Backports commit 978364f12adebb4b8d90fdeb71242cb3c1405740 from qemu
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Alistair Francis 2018-02-20 15:27:46 -05:00 committed by Lioncash
parent c31856e34e
commit 2945893f40
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 6 additions and 0 deletions
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6
qemu/target-arm/helper.c
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@ -929,6 +929,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
{ "PMOVSR", 15,9,12, 0,0,3, 0,
0, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pmovsr), {0, 0},
pmreg_access, NULL, pmovsr_write, NULL, raw_write },
{ "PMOVSCLR_EL0", 0,9,12, 3,3,3, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pmovsr), {0, 0},
pmreg_access, NULL, pmovsr_write, NULL, raw_write },
/* Unimplemented so WI. */
{ "PMSWINC", 15,9,12, 0,0,4, 0,
ARM_CP_NOP, PL0_W, 0, NULL, 0, 0, {0, 0},
@ -966,6 +969,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
{ "PMINTENCLR", 15,9,14, 0,0,2, 0,
ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0},
NULL, NULL, pmintenclr_write, },
{ "PMINTENCLR_EL1", 0,9,14, 3,0,2, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0},
NULL, NULL, pmintenclr_write },
{ "CCSIDR", 0,0,0, 3,1,0, ARM_CP_STATE_BOTH,
ARM_CP_NO_RAW, PL1_R, 0, NULL, 0, 0, {0, 0},
NULL, ccsidr_read, },