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target/riscv: Add the Hypervisor extension
Backports commit af1fa0039c799a350bcde07b3d8a71dfde07d11b from qemu
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@ -71,6 +71,7 @@
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#define RVC RV('C')
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#define RVS RV('S')
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#define RVU RV('U')
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#define RVH RV('H')
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/* S extension denotes that Supervisor mode exists, however it is possible
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to have a core that support S mode but does not have an MMU and there
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