target/riscv: Add the Hypervisor extension

Backports commit af1fa0039c799a350bcde07b3d8a71dfde07d11b from qemu
This commit is contained in:
Alistair Francis 2020-03-22 01:01:06 -04:00 committed by Lioncash
parent 83ac8747a5
commit 40afe12008

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@ -71,6 +71,7 @@
#define RVC RV('C')
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there