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target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR

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The registers MVBAR and SCR should have the behaviour of trapping to
EL3 if accessed from Secure EL1, but we were incorrectly implementing
them to UNDEF (which would trap to EL1). Fix this by using the new
access_trap_aa32s_el1() access function.

Backports commit efe4a274083f61484a8f1478d93f229d43aa8095 from qemu
This commit is contained in:
Peter Maydell 2018-02-20 11:10:34 -05:00 committed by Lioncash
parent c0411e5422
commit 4552444928
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 4 additions and 4 deletions
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8
qemu/target-arm/helper.c
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@ -3079,8 +3079,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.scr_el3), {0, 0},
NULL, NULL, scr_write },
{ "SCR", 15,1,1, 0,0,0, 0,ARM_CP_ALIAS,
PL3_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.scr_el3), {0, 0},
NULL, NULL, scr_write, NULL, NULL, NULL },
PL1_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.scr_el3), {0, 0},
access_trap_aa32s_el1, NULL, scr_write, NULL, NULL, NULL },
{ "MDCR_EL3", 0,1,3, 3,6,1, ARM_CP_STATE_AA64, 0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mdcr_el3) },
{ "SDCR", 15,1,3, 0,0,1, 0, ARM_CP_ALIAS,
@ -3094,8 +3094,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
{ "NSACR", 15,1,1, 0,0,2, 0,0,
PL3_W | PL1_R, 0, NULL, 0, offsetof(CPUARMState, cp15.nsacr) },
{ "MVBAR", 15,12,0, 0,0,1, 0,0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mvbar), {0, 0},
NULL, NULL, vbar_write },
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mvbar), {0, 0},
access_trap_aa32s_el1, NULL, vbar_write },
{ "SCTLR_EL3", 0,1,0, 3,6,0, ARM_CP_STATE_AA64,
ARM_CP_ALIAS, /* reset handled by AArch32 view */
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.sctlr_el[3]), {0, 0},