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target/mips: Correct the second argument type of cpu_supports_isa()

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"insn_flags" bitfield was expanded from 32-bit to 64-bit in commit
f9c9cd63e3. However, this was not reflected on the second argument
of the function cpu_supports_isa(). By chance, this did not create
some wrong behavior, since the left-most halves of all instances of
the second argument are currently all zeros. However, this is still
a bug waiting to happen. Correct this by changing the type of the
second argument to be always 64-bit.

Backports commit 5b1e098128367d6ef7cb2d1e99a55fcf4fa9cdde from qemu
This commit is contained in:
Aleksandar Markovic 2019-01-25 12:45:19 -05:00 committed by Lioncash
parent fc2e767e17
commit 49e7e28ec9
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 2 additions and 2 deletions
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2
qemu/target/mips/cpu.h
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@ -1173,7 +1173,7 @@ enum {
#define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
bool cpu_supports_isa(struct uc_struct *uc, const char *cpu_model, unsigned int isa);
bool cpu_supports_isa(struct uc_struct *uc, const char *cpu_model, uint64_t isa);
bool cpu_supports_cps_smp(struct uc_struct *uc, const char *cpu_type);
void cpu_set_exception_base(struct uc_struct *uc, int vp_index, target_ulong address);

2
qemu/target/mips/translate.c
View file

@ -30068,7 +30068,7 @@ bool cpu_supports_cps_smp(struct uc_struct *uc, const char *cpu_type)
return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
}
bool cpu_supports_isa(struct uc_struct *uc, const char *cpu_type, unsigned int isa)
bool cpu_supports_isa(struct uc_struct *uc, const char *cpu_type, uint64_t isa)
{
const MIPSCPUClass *mcc = MIPS_CPU_CLASS(uc, object_class_by_name(uc, cpu_type));
return (mcc->cpu_def->insn_flags & isa) != 0;