yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-03-23 06:25:12 +00:00
Code Issues Packages Projects Releases Wiki Activity

target-arm: Add support for PMU register PMINTENSET_EL1

Browse source 
This patch adds access support for PMINTENSET_EL1.

Backports commit e6ec54571e424bb1d6e50e32fe317c616cde3e05 from qemu
This commit is contained in:
Wei Huang 2018-03-02 07:57:36 -05:00 committed by Lioncash
parent 3b34b7f0f9
commit 5e3349a818
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 6 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
qemu/target/arm/cpu.h
View file

@ -313,7 +313,7 @@ typedef struct CPUARMState {
uint32_t c9_pmovsr; /* perf monitor overflow status */
uint32_t c9_pmuserenr; /* perf monitor user enable */
uint64_t c9_pmselr; /* perf monitor counter selection register */
uint32_t c9_pminten; /* perf monitor interrupt enables */
uint64_t c9_pminten; /* perf monitor interrupt enables */
union { /* Memory attribute redirection */
struct {
#ifdef HOST_WORDS_BIGENDIAN

7
qemu/target/arm/helper.c
View file

@ -1128,8 +1128,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
{ "PMUSERENR_EL0", 0,9,14,3,3,0, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
PL0_R | PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pmuserenr), {0, 0},
access_tpm, NULL, pmuserenr_write, NULL, raw_write },
{ "PMINTENSET", 15,9,14, 0,0,1, 0,
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0},
{ "PMINTENSET", 15,9,14, 0,0,1, 0, ARM_CP_ALIAS,
PL1_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.c9_pminten), {0, 0},
access_tpm, NULL, pmintenset_write, NULL, raw_write },
{ "PMINTENSET_EL1", 0,9,14, 3,0,1, ARM_CP_STATE_AA64, ARM_CP_IO,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0},
access_tpm, NULL, pmintenset_write, NULL, raw_write },
{ "PMINTENCLR", 15,9,14, 0,0,2, 0,
ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0},