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target-arm: lpae: Move declaration of t0sz and t1sz

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Move declaration of t0sz and t1sz to the top of the function
avoiding a mix of code and variable declarations.

No functional change.

Backports commit 1f4c8c18a5b6f4fad13e13b7e3828124c6c8f34d from qemu
This commit is contained in:
Edgar E. Iglesias 2018-02-17 13:14:30 -05:00 committed by Lioncash
parent 0c1c636b96
commit 7be3cda1ea
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 3 additions and 2 deletions
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5
qemu/target-arm/helper.c
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@ -5831,6 +5831,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
MMUFaultType fault_type = translation_fault;
uint32_t level = 1;
uint32_t epd = 0;
int32_t t0sz, t1sz;
int32_t tsz;
uint32_t tg;
uint64_t ttbr;
@ -5886,12 +5887,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
* This is a Non-secure PL0/1 stage 1 translation, so controlled by
* TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
*/
int32_t t0sz = extract32(tcr->raw_tcr, 0, 6);
t0sz = extract32(tcr->raw_tcr, 0, 6);
if (va_size == 64) {
t0sz = MIN(t0sz, 39);
t0sz = MAX(t0sz, 16);
}
int32_t t1sz = extract32(tcr->raw_tcr, 16, 6);
t1sz = extract32(tcr->raw_tcr, 16, 6);
if (va_size == 64) {
t1sz = MIN(t1sz, 39);
t1sz = MAX(t1sz, 16);