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target/riscv: vector floating-point/integer type-convert instructions

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Backports 921009732614fd620c75f05496597796719544cf
This commit is contained in:
LIU Zhiwei 2021-03-07 12:00:34 -05:00 committed by Lioncash
parent fabc8bab77
commit 8b06759ba4
7 changed files with 92 additions and 0 deletions
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12
qemu/header_gen.py
View file

@ -7169,6 +7169,18 @@ riscv_symbols = (
'helper_vfmerge_vfm_h',
'helper_vfmerge_vfm_w',
'helper_vfmerge_vfm_d',
'helper_vfcvt_xu_f_v_h',
'helper_vfcvt_xu_f_v_w',
'helper_vfcvt_xu_f_v_d',
'helper_vfcvt_x_f_v_h',
'helper_vfcvt_x_f_v_w',
'helper_vfcvt_x_f_v_d',
'helper_vfcvt_f_xu_v_h',
'helper_vfcvt_f_xu_v_w',
'helper_vfcvt_f_xu_v_d',
'helper_vfcvt_f_x_v_h',
'helper_vfcvt_f_x_v_w',
'helper_vfcvt_f_x_v_d',
'pmp_hart_has_privs',
'pmpaddr_csr_read',
'pmpaddr_csr_write',

12
qemu/riscv32.h
View file

@ -4605,6 +4605,18 @@
#define helper_vfmerge_vfm_h helper_vfmerge_vfm_h_riscv32
#define helper_vfmerge_vfm_w helper_vfmerge_vfm_w_riscv32
#define helper_vfmerge_vfm_d helper_vfmerge_vfm_d_riscv32
#define helper_vfcvt_xu_f_v_h helper_vfcvt_xu_f_v_h_riscv32
#define helper_vfcvt_xu_f_v_w helper_vfcvt_xu_f_v_w_riscv32
#define helper_vfcvt_xu_f_v_d helper_vfcvt_xu_f_v_d_riscv32
#define helper_vfcvt_x_f_v_h helper_vfcvt_x_f_v_h_riscv32
#define helper_vfcvt_x_f_v_w helper_vfcvt_x_f_v_w_riscv32
#define helper_vfcvt_x_f_v_d helper_vfcvt_x_f_v_d_riscv32
#define helper_vfcvt_f_xu_v_h helper_vfcvt_f_xu_v_h_riscv32
#define helper_vfcvt_f_xu_v_w helper_vfcvt_f_xu_v_w_riscv32
#define helper_vfcvt_f_xu_v_d helper_vfcvt_f_xu_v_d_riscv32
#define helper_vfcvt_f_x_v_h helper_vfcvt_f_x_v_h_riscv32
#define helper_vfcvt_f_x_v_w helper_vfcvt_f_x_v_w_riscv32
#define helper_vfcvt_f_x_v_d helper_vfcvt_f_x_v_d_riscv32
#define pmp_hart_has_privs pmp_hart_has_privs_riscv32
#define pmpaddr_csr_read pmpaddr_csr_read_riscv32
#define pmpaddr_csr_write pmpaddr_csr_write_riscv32

12
qemu/riscv64.h
View file

@ -4605,6 +4605,18 @@
#define helper_vfmerge_vfm_h helper_vfmerge_vfm_h_riscv64
#define helper_vfmerge_vfm_w helper_vfmerge_vfm_w_riscv64
#define helper_vfmerge_vfm_d helper_vfmerge_vfm_d_riscv64
#define helper_vfcvt_xu_f_v_h helper_vfcvt_xu_f_v_h_riscv64
#define helper_vfcvt_xu_f_v_w helper_vfcvt_xu_f_v_w_riscv64
#define helper_vfcvt_xu_f_v_d helper_vfcvt_xu_f_v_d_riscv64
#define helper_vfcvt_x_f_v_h helper_vfcvt_x_f_v_h_riscv64
#define helper_vfcvt_x_f_v_w helper_vfcvt_x_f_v_w_riscv64
#define helper_vfcvt_x_f_v_d helper_vfcvt_x_f_v_d_riscv64
#define helper_vfcvt_f_xu_v_h helper_vfcvt_f_xu_v_h_riscv64
#define helper_vfcvt_f_xu_v_w helper_vfcvt_f_xu_v_w_riscv64
#define helper_vfcvt_f_xu_v_d helper_vfcvt_f_xu_v_d_riscv64
#define helper_vfcvt_f_x_v_h helper_vfcvt_f_x_v_h_riscv64
#define helper_vfcvt_f_x_v_w helper_vfcvt_f_x_v_w_riscv64
#define helper_vfcvt_f_x_v_d helper_vfcvt_f_x_v_d_riscv64
#define pmp_hart_has_privs pmp_hart_has_privs_riscv64
#define pmpaddr_csr_read pmpaddr_csr_read_riscv64
#define pmpaddr_csr_write pmpaddr_csr_write_riscv64

13
qemu/target/riscv/helper.h
View file

@ -1007,3 +1007,16 @@ DEF_HELPER_5(vfclass_v_d, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfmerge_vfm_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfmerge_vfm_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfmerge_vfm_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_5(vfcvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_xu_f_v_d, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_x_f_v_d, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_f_xu_v_d, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfcvt_f_x_v_d, void, ptr, ptr, ptr, env, i32)

4
qemu/target/riscv/insn32.decode
View file

@ -517,6 +517,10 @@ vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm
vfcvt_x_f_v 100010 . ..... 00001 001 ..... 1010111 @r2_vm
vfcvt_f_xu_v 100010 . ..... 00010 001 ..... 1010111 @r2_vm
vfcvt_f_x_v 100010 . ..... 00011 001 ..... 1010111 @r2_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r

6
qemu/target/riscv/insn_trans/trans_rvv.inc.c
View file

@ -2257,3 +2257,9 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
}
return false;
}
/* Single-Width Floating-Point/Integer Type-Convert Instructions */
GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check)
GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check)
GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check)
GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check)

33
qemu/target/riscv/vector_helper.c
View file

@ -4194,3 +4194,36 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2, clearh)
GEN_VFMERGE_VF(vfmerge_vfm_w, int32_t, H4, clearl)
GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8, clearq)
/* Single-Width Floating-Point/Integer Type-Convert Instructions */
/* vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */
RVVCALL(OPFVV1, vfcvt_xu_f_v_h, OP_UU_H, H2, H2, float16_to_uint16)
RVVCALL(OPFVV1, vfcvt_xu_f_v_w, OP_UU_W, H4, H4, float32_to_uint32)
RVVCALL(OPFVV1, vfcvt_xu_f_v_d, OP_UU_D, H8, H8, float64_to_uint64)
GEN_VEXT_V_ENV(vfcvt_xu_f_v_h, 2, 2, clearh)
GEN_VEXT_V_ENV(vfcvt_xu_f_v_w, 4, 4, clearl)
GEN_VEXT_V_ENV(vfcvt_xu_f_v_d, 8, 8, clearq)
/* vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. */
RVVCALL(OPFVV1, vfcvt_x_f_v_h, OP_UU_H, H2, H2, float16_to_int16)
RVVCALL(OPFVV1, vfcvt_x_f_v_w, OP_UU_W, H4, H4, float32_to_int32)
RVVCALL(OPFVV1, vfcvt_x_f_v_d, OP_UU_D, H8, H8, float64_to_int64)
GEN_VEXT_V_ENV(vfcvt_x_f_v_h, 2, 2, clearh)
GEN_VEXT_V_ENV(vfcvt_x_f_v_w, 4, 4, clearl)
GEN_VEXT_V_ENV(vfcvt_x_f_v_d, 8, 8, clearq)
/* vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. */
RVVCALL(OPFVV1, vfcvt_f_xu_v_h, OP_UU_H, H2, H2, uint16_to_float16)
RVVCALL(OPFVV1, vfcvt_f_xu_v_w, OP_UU_W, H4, H4, uint32_to_float32)
RVVCALL(OPFVV1, vfcvt_f_xu_v_d, OP_UU_D, H8, H8, uint64_to_float64)
GEN_VEXT_V_ENV(vfcvt_f_xu_v_h, 2, 2, clearh)
GEN_VEXT_V_ENV(vfcvt_f_xu_v_w, 4, 4, clearl)
GEN_VEXT_V_ENV(vfcvt_f_xu_v_d, 8, 8, clearq)
/* vfcvt.f.x.v vd, vs2, vm # Convert integer to float. */
RVVCALL(OPFVV1, vfcvt_f_x_v_h, OP_UU_H, H2, H2, int16_to_float16)
RVVCALL(OPFVV1, vfcvt_f_x_v_w, OP_UU_W, H4, H4, int32_to_float32)
RVVCALL(OPFVV1, vfcvt_f_x_v_d, OP_UU_D, H8, H8, int64_to_float64)
GEN_VEXT_V_ENV(vfcvt_f_x_v_h, 2, 2, clearh)
GEN_VEXT_V_ENV(vfcvt_f_x_v_w, 4, 4, clearl)
GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8, clearq)