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target/arm: Implement ARMv8.5-CondM
Backports commit 5ef84f111483e3f7b57efc690e22081ca8f99544 from qemu
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1dfa15a683
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@ -3416,6 +3416,11 @@ static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
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return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
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return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
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}
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}
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static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
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}
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static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
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static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
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{
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{
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
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return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
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@ -254,7 +254,7 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, TS, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
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cpu->isar.id_aa64isar0 = t;
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cpu->isar.id_aa64isar0 = t;
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t = cpu->isar.id_aa64isar1;
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t = cpu->isar.id_aa64isar1;
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@ -1721,6 +1721,51 @@ static void handle_sync(DisasContext *s, uint32_t insn,
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}
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}
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}
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}
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static void gen_xaflag(DisasContext *s)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_i32 z = tcg_temp_new_i32(tcg_ctx);
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tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, z, tcg_ctx->cpu_ZF, 0);
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/*
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* (!C & !Z) << 31
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* (!(C | Z)) << 31
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* ~((C | Z) << 31)
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* ~-(C | Z)
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* (C | Z) - 1
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*/
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tcg_gen_or_i32(tcg_ctx, tcg_ctx->cpu_NF, tcg_ctx->cpu_CF, z);
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tcg_gen_subi_i32(tcg_ctx, tcg_ctx->cpu_NF, tcg_ctx->cpu_NF, 1);
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/* !(Z & C) */
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tcg_gen_and_i32(tcg_ctx, tcg_ctx->cpu_ZF, z, tcg_ctx->cpu_CF);
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tcg_gen_xori_i32(tcg_ctx, tcg_ctx->cpu_ZF, tcg_ctx->cpu_ZF, 1);
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/* (!C & Z) << 31 -> -(Z & ~C) */
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tcg_gen_andc_i32(tcg_ctx, tcg_ctx->cpu_VF, z, tcg_ctx->cpu_CF);
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tcg_gen_neg_i32(tcg_ctx, tcg_ctx->cpu_VF, tcg_ctx->cpu_VF);
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/* C | Z */
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tcg_gen_or_i32(tcg_ctx, tcg_ctx->cpu_CF, tcg_ctx->cpu_CF, z);
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tcg_temp_free_i32(tcg_ctx, z);
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}
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static void gen_axflag(DisasContext *s)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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tcg_gen_sari_i32(tcg_ctx, tcg_ctx->cpu_VF, tcg_ctx->cpu_VF, 31); /* V ? -1 : 0 */
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tcg_gen_andc_i32(tcg_ctx, tcg_ctx->cpu_CF, tcg_ctx->cpu_CF, tcg_ctx->cpu_VF); /* C & !V */
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/* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
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tcg_gen_andc_i32(tcg_ctx, tcg_ctx->cpu_ZF, tcg_ctx->cpu_ZF, tcg_ctx->cpu_VF);
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tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_NF, 0);
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tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_VF, 0);
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}
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/* MSR (immediate) - move immediate to processor state field */
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/* MSR (immediate) - move immediate to processor state field */
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static void handle_msr_i(DisasContext *s, uint32_t insn,
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static void handle_msr_i(DisasContext *s, uint32_t insn,
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unsigned int op1, unsigned int op2, unsigned int crm)
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unsigned int op1, unsigned int op2, unsigned int crm)
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@ -1741,6 +1786,22 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
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s->base.is_jmp = DISAS_NEXT;
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s->base.is_jmp = DISAS_NEXT;
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break;
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break;
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case 0x01: /* XAFlag */
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if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {
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goto do_unallocated;
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}
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gen_xaflag(s);
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s->base.is_jmp = DISAS_NEXT;
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break;
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case 0x02: /* AXFlag */
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if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {
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goto do_unallocated;
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}
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gen_axflag(s);
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s->base.is_jmp = DISAS_NEXT;
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break;
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case 0x05: /* SPSel */
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case 0x05: /* SPSel */
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if (s->current_el == 0) {
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if (s->current_el == 0) {
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goto do_unallocated;
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goto do_unallocated;
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