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target-arm: Correct bad VBAR patch merge

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Lioncash 2018-02-20 15:34:21 -05:00
parent 2945893f40
commit b29e024f56
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 4 additions and 11 deletions
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15
qemu/target-arm/helper.c
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@ -972,6 +972,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
{ "PMINTENCLR_EL1", 0,9,14, 3,0,2, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0},
NULL, NULL, pmintenclr_write },
{ "VBAR", 0,12,0, 3,0,0, ARM_CP_STATE_BOTH, 0,
PL1_RW, 0, NULL, 0, 0,
{ offsetof(CPUARMState, cp15.vbar_s), offsetof(CPUARMState, cp15.vbar_ns) },
NULL, NULL, vbar_write, },
{ "CCSIDR", 0,0,0, 3,1,0, ARM_CP_STATE_BOTH,
ARM_CP_NO_RAW, PL1_R, 0, NULL, 0, 0, {0, 0},
NULL, ccsidr_read, },
@ -4106,17 +4110,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
}
if (arm_feature(env, ARM_FEATURE_VBAR)) {
ARMCPRegInfo vbar_cp_reginfo[] = {
{ "VBAR", 0,12,0, 3,0,0, ARM_CP_STATE_BOTH,
0, PL1_RW, 0, NULL, 0, 0,
{ offsetof(CPUARMState, cp15.vbar_s), offsetof(CPUARMState, cp15.vbar_ns) },
NULL, NULL, vbar_write, },
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, vbar_cp_reginfo);
}
/* Generic registers whose values depend on the implementation */
{
ARMCPRegInfo sctlr = {