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target-*: Increment num_insns immediately after tcg_gen_insn_start

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This does tidy the icount test common to all targets.

Backports commit 959082fc4a93a016a6b697e1e0c2b373d8a3a373 from qemu
This commit is contained in:
Richard Henderson 2018-02-11 12:45:22 -05:00 committed by Lioncash
parent a64d0ff657
commit dd1ec408e5
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GPG key ID: 4E3C3CC1031BA9C7
6 changed files with 14 additions and 15 deletions
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6
qemu/target-arm/translate-a64.c
View file

@ -11280,8 +11280,9 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
//tcg_ctx->gen_opc_icount[lj] = num_insns;
}
tcg_gen_insn_start(tcg_ctx, dc->pc);
num_insns++;
//if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
//if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
// gen_io_start();
//}
@ -11296,7 +11297,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
* "did not step an insn" case, and so the syndrome ISV and EX
* bits should be zero.
*/
assert(num_insns == 0);
assert(num_insns == 1);
gen_exception(dc, EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0));
dc->is_jmp = DISAS_EXC;
break;
@ -11314,7 +11315,6 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
* Also stop translation when a page boundary is reached. This
* ensures prefetch aborts occur at the right place.
*/
num_insns++;
} while (!dc->is_jmp && !tcg_op_buf_full(tcg_ctx) &&
!cs->singlestep_enabled &&
!dc->ss_active &&

6
qemu/target-arm/translate.c
View file

@ -11478,8 +11478,9 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
//tcg_ctx->gen_opc_icount[lj] = num_insns;
}
tcg_gen_insn_start(tcg_ctx, dc->pc);
num_insns++;
//if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
//if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
// gen_io_start();
//}
@ -11494,7 +11495,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
* "did not step an insn" case, and so the syndrome ISV and EX
* bits should be zero.
*/
assert(num_insns == 0);
assert(num_insns == 1);
gen_exception(dc, EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0));
goto done_generating;
}
@ -11537,7 +11538,6 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
* Otherwise the subsequent code could get translated several times.
* Also stop translation when a page boundary is reached. This
* ensures prefetch aborts occur at the right place. */
num_insns ++;
} while (!dc->is_jmp && !tcg_op_buf_full(tcg_ctx) &&
!cs->singlestep_enabled &&
!dc->ss_active &&

4
qemu/target-i386/translate.c
View file

@ -8730,15 +8730,15 @@ static inline void gen_intermediate_code_internal(uint8_t *gen_opc_cc_op,
// tcg_ctx->gen_opc_icount[lj] = num_insns;
}
tcg_gen_insn_start(tcg_ctx, pc_start);
num_insns++;
//if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
//if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
// gen_io_start();
//}
// Unicorn: save current PC address to sync EIP
dc->prev_pc = pc_ptr;
pc_ptr = disas_insn(env, dc, pc_ptr);
num_insns++;
/* stop translation if indicated */
if (dc->is_jmp)
break;

4
qemu/target-m68k/translate.c
View file

@ -3137,14 +3137,14 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
//tcg_ctx.gen_opc_icount[lj] = num_insns;
}
tcg_gen_insn_start(tcg_ctx, s->pc);
num_insns++;
//if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
//if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
// gen_io_start();
//}
dc->insn_pc = dc->pc;
disas_m68k_insn(env, dc);
num_insns++;
} while (!dc->is_jmp && !tcg_op_buf_full(tcg_ctx) &&
!cs->singlestep_enabled &&
(pc_offset) < (TARGET_PAGE_SIZE - 32) &&

5
qemu/target-mips/translate.c
View file

@ -19256,8 +19256,9 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
tcg_ctx->gen_opc_icount[lj] = num_insns;
}
tcg_gen_insn_start(tcg_ctx, ctx->pc);
num_insns++;
//if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
//if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
// gen_io_start();
//}
@ -19319,8 +19320,6 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
}
ctx.pc += insn_bytes;
num_insns++;
/* Execute a branch and its delay slot as a single instruction.
This is what GDB expects and is consistent with what the
hardware does (e.g. if a delay slot instruction faults, the

4
qemu/target-sparc/translate.c
View file

@ -5443,8 +5443,9 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
}
}
tcg_gen_insn_start(tcg_ctx, dc->pc);
num_insns++;
//if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
//if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
// gen_io_start();
//}
@ -5459,7 +5460,6 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
}
disas_sparc_insn(dc, insn, true);
num_insns++;
if (dc->is_br)
break;