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target/arm: V8M should not imply V7VE

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Instantiating mps2-an505 (cortex-m33) will fail make check when
V7VE asserts that ID_ISAR0.Divide includes ARM division. It is
also wrong to include ARM_FEATURE_LPAE.

Backports commit 5256df880d1312a58472af3fb0a3c51e708f2161 from qemu
This commit is contained in:
Richard Henderson 2018-11-10 08:02:23 -05:00 committed by Lioncash
parent 1a714e97af
commit e5797bb0b7
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 6 additions and 2 deletions
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6
qemu/target/arm/cpu.c
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@ -593,7 +593,11 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
/* Some features automatically imply others: */ /* Some features automatically imply others: */
if (arm_feature(env, ARM_FEATURE_V8)) { if (arm_feature(env, ARM_FEATURE_V8)) {
set_feature(env, ARM_FEATURE_V7VE); if (arm_feature(env, ARM_FEATURE_M)) {
set_feature(env, ARM_FEATURE_V7);
} else {
set_feature(env, ARM_FEATURE_V7VE);
}
} }
if (arm_feature(env, ARM_FEATURE_V7VE)) { if (arm_feature(env, ARM_FEATURE_V7VE)) {
/* v7 Virtualization Extensions. In real hardware this implies /* v7 Virtualization Extensions. In real hardware this implies

2
qemu/target/arm/helper.c
View file

@ -4400,7 +4400,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
* define these regs. * define these regs.
*/ */
{ "ID_AA64PFR0_EL1", 0,0,4, 3,0,0, ARM_CP_STATE_AA64, { "ID_AA64PFR0_EL1", 0,0,4, 3,0,0, ARM_CP_STATE_AA64,
ARM_CP_NO_RAW, PL1_R, 0, NULL, cpu->id_aa64pfr0, 0, {0, 0}, ARM_CP_NO_RAW, PL1_R, 0, NULL, cpu->isar.id_aa64pfr0, 0, {0, 0},
NULL, id_aa64pfr0_read, arm_cp_write_ignore }, NULL, id_aa64pfr0_read, arm_cp_write_ignore },
{ "ID_AA64PFR1_EL1", 0,0,4, 3,0,1, ARM_CP_STATE_AA64, { "ID_AA64PFR1_EL1", 0,0,4, 3,0,1, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->isar.id_aa64pfr1}, ARM_CP_CONST, PL1_R, 0, NULL, cpu->isar.id_aa64pfr1},