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Author SHA1 Message Date
Jonathon Reinhart 1be8ef69c8 add 'test' to main Makefile 2015-09-20 22:16:48 -04:00
Jonathon Reinhart 46ee860084 update to new error constants and silence printfs 2015-09-20 22:16:48 -04:00
Jonathon Reinhart 7a98fc4e78 add tests to test_x86.c from samples/ 2015-09-20 21:13:22 -04:00
Jonathon Reinhart c026c23efb add more mem map API tests 2015-09-20 21:13:22 -04:00
Jonathon Reinhart 4dae31b25e add uc_assert_(err|fail) macros 2015-09-20 21:13:22 -04:00
Jonathon Reinhart df3966a90c continued work on test framework 2015-09-20 21:13:22 -04:00
Jonathon Reinhart d4de54601d add start of test_mem_map.c 2015-09-20 21:13:22 -04:00
Jonathon Reinhart 12909e6a4c add basic cmocka unit test 2015-09-20 21:13:22 -04:00
Nguyen Anh Quynh ad835459bd fix conflicts when merging new_regress to master 2015-09-20 00:21:20 +07:00
Nguyen Anh Quynh 9aa04d9496 tb_gen_code(): only check to link next page if tb->size > 0 (so we skip empty block) 2015-09-20 00:05:17 +07:00
Nguyen Anh Quynh 7ab8d667fd fix regress/fpu_mem_write.py so it really emulates code 2015-09-20 00:02:30 +07:00
Nguyen Anh Quynh 4d45f11a08 regress/regress.py can be run from inside regress/ 2015-09-19 17:06:50 +07:00
danghvu cbb2cf3618 Regress python testcases must define expected value via unittest 2015-09-17 15:45:15 -05:00
danghvu 8c163706e4 Fix issue #113, untracked reference 2015-09-16 21:33:01 -05:00
Nguyen Anh Quynh 5005b4a6e2 arm: early check to see if the address of this block is the until address 2015-09-17 09:16:57 +07:00
Nguyen Anh Quynh d6b9c31dc9 sparc: more cleanup 2015-09-16 16:04:12 +07:00
Nguyen Anh Quynh f36bd83f85 cleanup regress/sparc*.py 2015-09-16 15:46:10 +07:00
mothran 893e6abcbd first atttempt at SPARC64 fixes, no longer SEGV's, set CPU model to: Sun UltraSparc IV 2015-09-15 23:12:03 -07:00
Nguyen Anh Quynh fe807952d0 bindings: update Sparc registers after the last core change 2015-09-15 14:17:57 +07:00
Nguyen Anh Quynh e581b8ea0e Merge branch 'master' of https://github.com/unicorn-engine/unicorn 2015-09-15 14:17:10 +07:00
Nguyen Anh Quynh 7eaedc5c15 add a comment for Arm instruction in regress/arm_movr12_hang.py 2015-09-15 14:16:57 +07:00
Nguyen Anh Quynh 163e49bf59 Merge pull request #141 from mothran/sparc_regs 
Updated sparc register system
 2015-09-15 14:14:46 +07:00
mothran 6962126707 update sparc_reg.py with %i registers 2015-09-14 23:28:09 -07:00
mothran d1e19df64e update the sparc_reg to test all g/o/l registers 2015-09-14 23:05:33 -07:00
mothran 69d73aa845 added emulated SPARC code for regress/sparc_reg.py, appears to be a bug in G and I registers 2015-09-14 21:23:42 -07:00
mothran 1638372793 fix small whitespace issue 2015-09-14 20:48:31 -07:00
mothran f4894a1c77 removed unneed cases in the switch statement 2015-09-14 20:44:50 -07:00
mothran d4d5631181 updated the sparc.h header so the alignment of certain registers was correct 2015-09-14 20:42:41 -07:00
mothran 6b521e9e9b update the sparc reg read/write to include o/l/i registers 2015-09-14 20:03:32 -07:00
mothran 85b3594c7c Merge branch 'master' of github.com:unicorn-engine/unicorn into sparc_regs 2015-09-14 19:57:23 -07:00
Nguyen Anh Quynh 3f726d1c57 chmod +x regress/sparc64.py 2015-09-14 09:46:05 +07:00
mothran 7dc41a8e4e update the regwptr upon reset 2015-09-13 18:10:28 -07:00
Nguyen Anh Quynh 507fc4dab7 Merge pull request #137 from mothran/sparc64_crash 
added the sparc64 crash regression
 2015-09-13 09:34:20 +08:00
mothran 2789e7951b added the sparc64 crash regression 2015-09-12 10:35:50 -07:00
mothran 657a6c3e25 modified the sparc reg get/set functions to use the current reg window ptr 2015-09-12 10:29:35 -07:00
mothran afecfee565 added SPARC sp / fp registers, also updated uint32_t's to uint64_t's in SPARC64 2015-09-10 23:20:52 -07:00
Nguyen Anh Quynh 548355acca sparc: do not accept BIGENDIAN mode in samples. more sanity check should be done in the core 2015-09-11 14:02:27 +08:00
Nguyen Anh Quynh b306fa65bd Merge pull request #135 from lunixbochs/test-133 
add test for #133
 2015-09-10 01:17:15 +08:00
Ryan Hileman 586d5ca9f8 add test for #133 2015-09-09 08:27:13 -07:00
Nguyen Anh Quynh 113245e12a fix some comments in unicorn.h 2015-09-09 17:00:00 +08:00
Nguyen Anh Quynh 39ac1bcb4e rename UC_ERR_INVAL to UC_ERR_ARG 2015-09-09 16:54:47 +08:00
Nguyen Anh Quynh d7ef204398 rename error codes ERR_MEM_READ, ERR_MEM_WRITE, ERR_MEM_FETCH 2015-09-09 16:25:48 +08:00
Nguyen Anh Quynh d3d38d3f21 handle read/write/fetch from unaligned addresses. this adds new error codes UC_ERR_READ_UNALIGNED, UC_ERR_WRITE_UNALIGNED & UC_ERR_FETCH_UNALIGNED 2015-09-09 15:52:15 +08:00
Nguyen Anh Quynh 6b52be24a3 fix regress/mips_except.py 2015-09-09 15:32:31 +08:00
Nguyen Anh Quynh 18b6680e96 mips: disable debug output 2015-09-08 23:56:25 +08:00
Nguyen Anh Quynh 99379e92e9 Merge pull request #131 from lunixbochs/mips-exception 
add regress for #130
 2015-09-08 15:47:53 +08:00
Ryan Hileman d134c62366 add regress for #130 2015-09-08 00:44:14 -07:00
Nguyen Anh Quynh 09c66f2183 Merge pull request #129 from lunixbochs/master 
refactor Go bindings to be more idiomatic
 2015-09-08 15:32:13 +08:00
Ryan Hileman 9a0d80b84c refactor Go bindings to be more idiomatic 2015-09-08 00:04:27 -07:00
Nguyen Anh Quynh fda17cd377 java: rename UC_MEM_EXE to UC_MEM_FETCH 2015-09-08 12:57:40 +08:00