4 commits

Author	SHA1	Message	Date
LIU Zhiwei	7d0d7338c2	target/riscv: add vector amo operations ... Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Backports 268fcca66bde62257960ec8d859de374315a5e3d	2021-02-26 09:47:32 -05:00
Bastian Koppelmann	7475207aba	target/riscv: Convert RV64D insns to decodetree ... Backports commit 31fe4d35f2608daecb2319c81e0bb4af81b398ae from qemu	2019-03-18 16:57:16 -04:00
Bastian Koppelmann	d8d107ec85	target/riscv: Convert RV64F insns to decodetree ... Backports commit 95561ee3b41a536cc373e59da10605e2a8676ee2 from qemu	2019-03-18 16:43:17 -04:00
Bastian Koppelmann	9edaf2069e	target/riscv: Convert RV32F insns to decodetree ... Backports commit 6f0e74ff4b7f83901e99e59108eaa43513a0ce36 from qemu	2019-03-18 16:40:04 -04:00