Richard Henderson
7c32498b7f
target/arm: Use tcg_gen_gvec_bitsel
...
This replaces 3 target-specific implementations for BIT, BIF, and BSL.
Backports commit 3a7a2b4e5cf0d49cd8b14e8225af0310068b7d20 from qemu
2019-06-13 16:12:56 -04:00
Lioncash
47b45f1bc2
arm: Take DisasContext as a parameter instead of TCGContext where applicable
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This is more future-friendly with qemu, as it's more generic.
2018-10-06 04:17:12 -04:00
Richard Henderson
4dc2b5ea79
target/arm: Extend vec_reg_offset to larger sizes
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Rearrange the arithmetic so that we are agnostic about the total size
of the vector and the size of the element. This will allow us to index
up to the 32nd byte and with 16-byte elements.
Backports commit 66f2dbd783d0b6172043e3679171421b2d0bac11 from qemu
2018-06-15 12:23:35 -04:00
Richard Henderson
d2d8e2fc33
target/arm: Introduce translate-a64.h
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Move some stuff that will be common to both translate-a64.c
and translate-sve.c.
Backports commit 8c71baedb8055beaa681823206ee3a74f9f8649a from qemu
2018-05-20 00:34:25 -04:00
