Commit graph

3 commits

Author SHA1 Message Date
Philippe Mathieu-Daudé b7ab3c861d
util/cacheinfo: Add missing include for ppc linux
This include was forgotten when splitting cacheinfo.c out of
tcg/ppc/tcg-target.inc.c (see commit b255b2c8).

For a Centos7 host, the include path

<signal.h>
<bits/sigcontext.h>
<asm/sigcontext.h>
<asm/elf.h>
<asm/auxvec.h>

implicitly pulls in the desired AT_* defines.
Not so for Debian Jessie.

Backports commit 810d5cad4087236236e00fd3046a16adf26e9060 from qemu
2018-03-03 23:05:44 -05:00
Pranith Kumar 2141c777f1
util/cacheinfo: Fix warning generated by clang
Clang generates the following warning on aarch64 host:

CC util/cacheinfo.o
/home/pranith/qemu/util/cacheinfo.c:121:48: warning: value size does not match register size specified by the constraint and modifier [-Wasm-operand-widths]
asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr));
^
/home/pranith/qemu/util/cacheinfo.c:121:28: note: use constraint modifier "w"
asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr));
^~
%w0

Constraint modifier 'w' is not (yet?) accepted by gcc. Fix this by increasing the ctr size.

Backports commit 2ae96c157ab3155baf6595c08cf5d3fe3c023a60 from qemu
2018-03-03 22:04:12 -05:00
Emilio G. Cota 8e58c67968
util: add cacheinfo
Add helpers to gather cache info from the host at init-time.

For now, only export the host's I/D cache line sizes, which we
will use to improve cache locality to avoid false sharing.

Backports commit b255b2c8a5484742606e8760870ba3e14d0c9605 from qemu
2018-03-03 16:58:28 -05:00