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2885 commits 7 branches 6 tags 35 MiB
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30 commits

Author SHA1 Message Date
Lioncash a913b3e468
tcg: Make cpu_gpr a TCGv array 
Commit 5d4e1a1081d3f1ec2908ff0eaebe312389971ab4
allows making the type concrete
 2018-02-21 01:02:46 -05:00
Lioncash 1defc70341
tcg: Make cpu_PC a TCGv 
Commit 5d4e1a1081d3f1ec2908ff0eaebe312389971ab4
allows making the type concrete
 2018-02-21 00:47:13 -05:00
Lioncash 372e3307c5
tcg: Make bcond, btarget and cpu_dspctrl TCGv 
Commit 5d4e1a1081d3f1ec2908ff0eaebe312389971ab4
allows making the type concrete
 2018-02-21 00:45:59 -05:00
Lioncash baf25644dd
tcg: Make cpu_HI and cpu_LO a TCGv array 
Commit 5d4e1a1081d3f1ec2908ff0eaebe312389971ab4
allows making the type concrete
 2018-02-21 00:34:49 -05:00
Nguyen Anh Quynh e917c9de10 Merge branch 'master' into msvc2 2017-04-21 01:17:00 +08:00
Nguyen Anh Quynh cb44f77ac3 mips: fix uc_reg_read() for MIPS64 2017-04-12 22:06:26 +08:00
Nguyen Anh Quynh 094ca80092 fix conflicts 2017-03-30 12:23:24 +08:00
zhangwm ccdb0ff523 armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition. 2017-03-15 22:25:35 +08:00
Nguyen Anh Quynh c01dcf0a14 fix merge conflicts 2017-03-10 21:04:33 +08:00
Matt Thomas 2749b8412e fix register widths for MIPS64 reg_read/write (#775) 
* fix register widths for MIPS64 reg_read/write

* fix preprocessor typedef error for qemu/target-mips
 2017-03-08 08:40:30 +08:00
xorstream 69ae8f7987 Fix for MIPS issue. (#733) 2017-01-23 12:39:34 +08:00
xorstream 72a497bc14 Added MIPS support and projects for all samples. 2017-01-23 01:05:08 +11:00
xorstream 1aeaf5c40d This code should now build the x86_x64-softmmu part 2. 2017-01-19 22:50:28 +11:00
Chris Eagle fccbcfd4c2 revert to use of g_free to make future qemu integrations easier (#695) 
* revert to use of g_free to make future qemu integrations easier

* bracing
 2016-12-21 22:28:36 +08:00
Chris Eagle e46545f722 remove glib dependency by provide compatible replacements 2016-12-18 14:56:58 -08:00
Nguyen Anh Quynh b7cdbe7a88 Merge branch 'feat/reg_save_restore' of https://github.com/rhelmot/unicorn into rhelmot-feat/reg_save_restore 2016-10-07 09:57:07 +08:00
Ryan Hileman cb615fdba7 remove uc->cpus 2016-09-23 07:38:21 -07:00
Andrew Dutcher 0ef2b5fd71 New feature: registers can be bulk saved/restored in an opaque blob 2016-08-20 04:14:07 -07:00
danghvu 27e0699ef5 mips: Fix memleak 2016-07-09 20:16:00 -05:00
Ryan Hileman acd88856e1 add batched reg access 2016-04-04 20:51:38 -07:00
Hiroyuki UEKAWA c5888e5670 move macros in qemu/target-*/unicorn*.c to uc_priv.h 2016-03-02 12:43:02 +09:00
Hiroyuki UEKAWA 1cd3c3093b fix WRITE_BYTE_H 2016-03-02 10:51:50 +09:00
Nguyen Anh Quynh 5a04bcb115 allow to change PC during callback. this solves issue #210 2016-01-28 14:06:17 +08:00
Nguyen Anh Quynh 3a36e327ab support memory redirection, so the issue #217 is fixed 2015-10-27 14:37:03 +08:00
Nguyen Anh Quynh 84e3b5c897 cast all the values to write to registers in uc_reg_write() to unsigned type. this fixes issue #98 2015-09-04 11:17:08 +08:00
Jonathon Reinhart 15a774ac90 change uch to uc_struct (target-mips) 2015-08-26 09:02:16 -04:00
Jonathon Reinhart 9163bba812 restore mode of .[ch] files 
These were marked as executable in 5c3b6819, likely due to a Windows
filesystem being involved. This can be avoided:
http://stackoverflow.com/q/1580596/119527
 2015-08-24 21:19:12 -04:00
Chris Eagle 5c3b681945 Add const to uc_reg_write and derivitives 2015-08-24 09:42:50 -07:00
mothran a167f7c456 renames the register constants so unicorn and capstone can compile together 2015-08-23 21:36:33 -07:00
Nguyen Anh Quynh 344d016104 import 2015-08-21 15:04:50 +08:00