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356 commits

Author SHA1 Message Date
Ryan Hileman d39c20acfe Go: fix NewRegBatch([]int{}) (#831) 2017-05-12 09:39:04 +07:00
Ryan Hileman 37edadedec go: add faster RegBatch type (#822) 2017-05-06 22:32:35 +08:00
Samuel Groß 5385baba39 Implemented read and write access to the YMM registers (#819) 2017-05-05 09:02:58 +08:00
zhangwm 4a62409949 arm64eb: arm64 big endian also using little endian instructions. (#816) 
* arm64eb: arm64 big endian also using little endian instructions.

* arm64: using another example that depends on endians.

example:
1. store a word: 0x12345678
2. load a byte:
   * little endian : 0x78
   * big endian    : 0x12
 2017-05-04 20:00:48 +08:00
Ryan Hileman 187b470245 add arm64 CPACR_EL1 register support (#814) 2017-05-02 14:51:19 +08:00
David Zimmer 9eebd6daa3 vb bindings remove DYNLOAD (#812) 2017-04-27 20:43:47 +08:00
xorstream fa45a42c76 Removed MSVC binding. (#808) 2017-04-27 10:21:04 +08:00
Nguyen Anh Quynh 0109cd6c8a Merge branch 'master' into a64 2017-04-25 13:00:15 +08:00
Nguyen Anh Quynh 2bd40b9c91 update armeb & arm64eb samples 2017-04-25 12:55:26 +08:00
Nguyen Anh Quynh 09d14704a5 bindings: update after UC_VERSION_EXTRA change 2017-04-25 12:41:00 +08:00
zhangwm 2e973a13f0 arm64eb: add support for ARM64 big endian. 2017-04-24 23:30:01 +08:00
Nguyen Anh Quynh e917c9de10 Merge branch 'master' into msvc2 2017-04-21 01:17:00 +08:00
Nguyen Anh Quynh 5dbc640b9a bump UC_VERSION_EXTRA to 1 2017-04-20 14:14:24 +08:00
Nguyen Anh Quynh 7441cfe4e5 Update unicorn.py 
space
 2017-04-18 07:46:12 +08:00
tylerni7 4f07910eae handle not having a path (#798) 2017-04-18 07:44:48 +08:00
Nguyen Anh Quynh 094ca80092 fix conflicts 2017-03-30 12:23:24 +08:00
zhangwm d2740b17ce armeb: add C sample for armeb. 2017-03-13 23:19:09 +08:00
zhangwm d8fe34a2e8 armeb: Add support for ARM big endian. 2017-03-13 22:32:44 +08:00
Nguyen Anh Quynh c01dcf0a14 fix merge conflicts 2017-03-10 21:04:33 +08:00
feliam 0150ca24b1 Add support for ARM application flags - APSR register (#776) 2017-03-09 22:28:03 +08:00
stevielavern b3a5eae81c uc_reg_read & uc_reg_write now support ARM64 Neon registers (#774) 
* uc_reg_read & uc_reg_write now support ARM64 Neon registers

* Do not reuse uc_x86_xmm for uc_arm64_neon128. TODO: refactor both classes to use the same parent.
 2017-03-07 21:29:34 +08:00
Nguyen Anh Quynh 117b48c33c bindings: use diff -u in Makefile 2017-02-26 16:52:06 +08:00
Adrian Herrera c090f198ad Haskell bindings update (#767) 
* haskell: Properly handle invalid memory access

* haskell: source cleanup

* haskell: added support for batch reg read/write
 2017-02-26 09:27:35 +08:00
Nguyen Anh Quynh f4325f8c4e bindings: update to support X86 MSR id 2017-02-24 21:51:01 +08:00
Ahmed Samy 02e6c14e12 x86: add MSR API via reg API (#755) 
Writing / reading to model specific registers should be as easy as
calling a function, it's a bit stupid to write shell code and run them
just to write/read to a MSR, and even worse, you need more than just a
shellcode to read...

So, add a special register ID called UC_X86_REG_MSR, which should be
passed to uc_reg_write()/uc_reg_read() as the register ID, and then a
data structure which is uc_x86_msr (12 bytes), as the value (always), where:
	Byte	Value		Size
	0	MSR ID		4
	4       MSR val		8
 2017-02-24 21:37:19 +08:00
Nguyen Anh Quynh 6ea39f7d5a merge msvc with master 2017-02-24 10:39:36 +08:00
Sascha Schirra eb4dc61c66 Updated ruby bindings (#744) 
* added methods for uc_context_save, uc_context_restore

* added test for context_save

* changed version of the lib
 2017-01-29 08:13:17 +08:00
Nguyen Anh Quynh b616115df1 update ChangeLog 2017-01-25 12:00:18 +08:00
Nguyen Anh Quynh a735576dd3 python: support uc_mem_regions() API 2017-01-24 12:47:27 +08:00
xorstream 21c0580d63 Remove old project dir. 2017-01-22 15:50:28 +11:00
xorstream 45cefc2cf6 Sync with current msvc branch. 2017-01-22 15:49:14 +11:00
xorstream a868ad9dc7 Moved ./bindings/msvc_native into ./msvc 2017-01-22 11:38:48 +11:00
Nguyen Anh Quynh 40434f6081 Update config-host.h 
msvc: cleanup config-host.h
 2017-01-22 04:53:58 +08:00
Nguyen Anh Quynh 5a1e86d46b update Windows DLL dependency 2017-01-22 00:39:21 +08:00
xorstream 2ae2134402 Added prebuild script to remove generated files and started adding projects for other CPUs. (#725) 
* Changed some MSVC compatibility defines based on MSVC version.

* Added prebuild_script.bat to remove leftover configure generated files before building.

Also added project files and MSVC copies of configure generated files for all supported CPUs.
 2017-01-21 23:22:51 +08:00
xorstream 37ac0efcea Added prebuild_script.bat to remove leftover configure generated files before building. 
Also added project files and MSVC copies of configure generated files for all supported CPUs.
 2017-01-22 01:17:36 +11:00
Nguyen Anh Quynh 17f01469ad msvc_native: add .gitignore 2017-01-21 18:12:00 +08:00
xorstream 770c5616e2 Automated leading tab to spaces conversion. 2017-01-21 12:28:22 +11:00
xorstream df41c49e2d Fixed warning about {} initialisers. 2017-01-21 11:41:11 +11:00
xorstream 429bfca48e Fixes for MSVC native support to still work with GCC/GNU. 2017-01-21 01:07:10 +11:00
xorstream 00ca6b1a5f Save copies of generated qapi files. 2017-01-21 00:31:03 +11:00
xorstream 8840d5b42b Save copies of generated qapi files. 2017-01-21 00:30:50 +11:00
xorstream fac6a66860 platform.h move #3 2017-01-21 00:13:21 +11:00
xorstream 1aaf57ca54 Some more little edits to prepare for pull request. 2017-01-20 22:46:32 +11:00
xorstream 1fea4e6d87 Some small changes to clean up before pull request. 2017-01-20 22:34:14 +11:00
xorstream 5c7c8375f9 Unicorn interface working with test app in 32bit and 64bit builds 2. 2017-01-20 17:28:14 +11:00
xorstream 002151874a Unicorn interface working with test app in 32bit and 64bit builds. 2017-01-20 17:27:22 +11:00
xorstream 1aeaf5c40d This code should now build the x86_x64-softmmu part 2. 2017-01-19 22:50:28 +11:00
xorstream 37f9a248ea This code should now build the x86_x64-softmmu part. 2017-01-19 22:42:28 +11:00
xorstream d56d09e5e1 Merge remote-tracking branch 'unicorn-engine/master' into msvc_native 2017-01-16 17:26:12 +11:00