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24 commits

Author SHA1 Message Date
Atish Patra e54d0916ef target/riscv/pmp: Raise exception if no PMP entry is configured 
As per the privilege specification, any access from S/U mode should fail
if no pmp region is configured.

Backports d102f19a2085ac931cb998e6153b73248cca49f1
 2021-03-08 15:39:55 -05:00
Alistair Francis 416b2a0077 target/riscv: Split the Hypervisor execute load helpers 
Split the hypervisor execute load functions into two seperate functions.
This avoids us having to pass the memop to the C helper functions.

Backports 7687537ab0c16e0b1e69e7707456573a64b8e13b
 2021-03-08 15:14:47 -05:00
Alistair Francis 4762dcda3c target/riscv: Remove the hyp load and store functions 
Remove the special Virtulisation load and store functions and just use
the standard tcg tcg_gen_qemu_ld_tl() and tcg_gen_qemu_st_tl() functions
instead.

As part of this change we ensure we still run an access check to make
sure we can perform the operations.

Backports 743077b35b1ed88ed243daefafe9403d88a958f6
 2021-03-08 15:11:11 -05:00
Alistair Francis bd81c057ed target/riscv: Remove the HS_TWO_STAGE flag 
The HS_TWO_STAGE flag is no longer required as the MMU index contains
the information if we are performing a two stage access.

Backports 1c1c060aa866986ef8b7eb334abbb8c104a46e5c
 2021-03-08 15:03:15 -05:00
Alistair Francis e5a9b8fc17 target/riscv: Set the virtualised MMU mode when doing hyp accesses 
When performing the hypervisor load/store operations set the MMU mode to
indicate that we are virtualised.

Backports 3e5979046f3f5f65828d3950d0c3ec9846d63715
 2021-03-08 14:57:58 -05:00
Yifei Jiang 9d47840784 target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit 
mstatus/mstatush and vsstatus/vsstatush are two halved for RISCV32.
This patch expands mstatus and vsstatus to uint64_t instead of
target_ulong so that it can be saved as one unit and reduce some
ifdefs in the code.

Backports 284d697c74ef3f4210cbccc5cd6b4894740e4ab3
 2021-03-08 14:52:44 -05:00
Georg Kotheimer d2cea344f0 target/riscv: Fix implementation of HLVX.WU instruction 
The HLVX.WU instruction is supposed to read a machine word,
but prior to this change it read a byte instead.

Fixes: 8c5362acb57 ("target/riscv: Allow generating hlv/hlvx/hsv instructions")

Backports 1da46012eaaeb2feb3aa6a5a8fc0a03200b673aa
 2021-03-08 14:40:28 -05:00
Alistair Francis 4805f204d8 riscv: Convert interrupt logs to use qemu_log_mask() 
Currently we log interrupts and exceptions using the trace backend in
riscv_cpu_do_interrupt(). We also log exceptions using the interrupt log
mask (-d int) in riscv_raise_exception().

This patch converts riscv_cpu_do_interrupt() to log both interrupts and
exceptions with the interrupt log mask, so that both are printed when a
user runs QEMU with -d int.

Backports 69430111ab2fe3f32548a0e70437655d0d937a6a
 2021-03-08 14:37:08 -05:00
Alistair Francis 0e14547c7d target/riscv: Support the Virtual Instruction fault 
Backports e39a8320b088dd5efc9ebaafe387e52b3d962665
 2021-03-08 13:55:02 -05:00
Alistair Francis c3d9e15f02 target/riscv: Return the exception from invalid CSR accesses 
When performing a CSR access let's return a negative exception value on
an error instead of -1. This will allow us to specify the exception in
future patches.

Backports 57cb2083e638bb28616c059cbf067d99552a04bb
 2021-03-08 13:49:09 -05:00
Alistair Francis bf52a9b17e target/riscv: Update the Hypervisor trap return/entry 
Backports f2d5850f71f3e41b240f328c2bc844a4e44e66c9
 2021-03-08 13:31:03 -05:00
Alistair Francis 7ceb984b60 target/riscv: Don't allow guest to write to htinst 
Backports e2eb5ca8f66c239f6194afda88cad455e42725ef
 2021-03-08 13:22:51 -05:00
Alistair Francis 4972437f93 target/riscv: Allow generating hlv/hlvx/hsv instructions 
Backports 8c5362acb573b8b1913238a5ddefdeef12f513a8
 2021-03-08 13:13:32 -05:00
Alistair Francis e1f49dc888 target/riscv: Implement checks for hfence 
Call the helper_hyp_tlb_flush() function on hfence instructions which
will generate an illegal insruction execption if we don't have
permission to flush the Hypervisor level TLBs.

Backports commit 2761db5fc20943bbd606b6fd49640ac000398de6 from qemu
 2021-02-25 12:03:57 -05:00
Alistair Francis 2584ab8ee5 target/riscv: Drop support for ISA spec version 1.09.1 
The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since
4.1. It's not commonly used so let's remove support for it.

Backports commit 1a9540d1f1a9c5022d9273d0244e5809679dd33b from qemu
 2020-06-14 22:23:26 -04:00
Alistair Francis 1001f0ba1f target/riscv: Correctly implement TSR trap 
As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't
correctly handling illegal instructions based on the value of MSTATUS_TSR
and the current privledge level.

This patch fixes the issue raised in the bug by raising an illegal
instruction if TSR is set and we are in S-Mode.

Backports commit ed5abf46b3c414ef58e647145f19b3966700b206 from qemu
 2020-04-30 06:19:49 -04:00
Alistair Francis 6c3338430a target/riscv: Add the MSTATUS_MPV_ISSET helper macro 
Add a helper macro MSTATUS_MPV_ISSET() which will determine if the
MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V.

Backports commit e44b50b5b2e508fdd24915ab0e44ac49685e1de3 from qemu
 2020-03-22 02:18:02 -04:00
Alistair Francis 835b025692 target/riscv: Add support for the 32-bit MSTATUSH CSR 
Backports commit 551fa7e8a695ea5fd1cca8ffd318556855bbf54f from qemu
 2020-03-22 02:16:13 -04:00
Alistair Francis fcc30eac4d target/riscv: Add Hypervisor trap return support 
Backports commit e3fba4bab668a41f7cec6405c5aeb21497bd7c83 from qemu
 2020-03-22 01:41:58 -04:00
Alistair Francis f6b14e146e target/riscv: Generate illegal instruction on WFI when V=1 
Backports commit 9d0d11269671646be7475cc01142e9d3ed8ae59c from qemu
 2020-03-22 01:38:14 -04:00
Yiting Wang 1c7f2083da riscv: Set xPIE to 1 after xRET 
When executing an xRET instruction, supposing xPP holds the
value y, xIE is set to xPIE; the privilege mode is changed to y;
xPIE is set to 1. But QEMU sets xPIE to 0 incorrectly.

Backports commit a37f21c27d3e2342c2080aafd4cfe7e949612428 from qemu
 2020-03-21 12:18:59 -04:00
Richard Henderson 47b797f1bb
target/riscv: Use env_cpu, env_archcpu 
Cleanup in the boilerplate that each target must define.
Replace riscv_env_get_cpu with env_archcpu. The combination
CPU(riscv_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.

Backports commit 3109cd98a6c0c618189b38a83a8aa29cb20acbce from qemu
 2019-06-12 12:06:19 -04:00
Jonathan Behrens 25c0333213
target/riscv: Do not allow sfence.vma from user mode 
The 'sfence.vma' instruction is privileged, and should only ever be allowed
when executing in supervisor mode or higher.

Backports commit b86f4167630802128d94f3c89043d97d2f4c2546 from qemu
 2019-05-28 18:29:46 -04:00
Lioncash b6f752970b
target/riscv: Initial introduction of the RISC-V target 
This ports over the RISC-V architecture from Qemu. This is currently a
very barebones transition. No code hooking or any fancy stuff.
Currently, you can feed it instructions and query the CPU state itself.

This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit
is desirable through Unicorn's interface as well.

Extremely basic examples of executing a single instruction have been
added to the samples directory to help demonstrate how to use the basic
functionality.
 2019-03-08 21:46:10 -05:00