66 commits

Author	SHA1	Message	Date
James Hogan	e71d19df81	tcg/mips: Support r6 multiply/divide encodings ... MIPSr6 adds several new integer multiply, divide, and modulo instructions, and removes several pre-r6 encodings, along with the HI/LO registers which were the implicit operands of some of those instructions. Update TCG to use the new instructions when built for r6. The new instructions actually map much more directly to the TCG ops, as they only provide a single 32-bit half of the result and in a normal general purpose register instead of HI or LO. The mulu2_i32 and muls2_i32 operations are no longer appropriate for r6, so they are removed from the TCG opcode table. This is because they would need to emit two separate host instructions anyway (for the high and low half of the result), which TCG can arrange automatically for us in the absense of mulu2_i32/muls2_i32 by splitting it into mul_i32 and mul*h_i32 TCG ops. Backports commit bc6d0c22b09a72897d9db4482076f89e7de97400 from qemu	2018-02-17 15:24:04 -05:00
James Hogan	9dac598855	tcg/mips: Support r6 JR encoding ... MIPSr6 encodes JR as JALR with zero as the link register, and the pre-r6 JR encoding is removed. Update TCG to use the new encoding when built for r6. We still use the old encoding for pre-r6, so as not to confuse return prediction stack hardware which may detect only particular encodings of the return instruction. Backports commit 6e0d096989be52c2b945fc83a9bd15d887bbdb47 from qemu	2018-02-17 15:24:04 -05:00
James Hogan	7f1bc28513	tcg/mips: Add use_mips32r6_instructions definition ... Add definition use_mips32r6_instructions to the MIPS TCG backend which is constant 1 when built for MIPS release 6. This will be used to decide between pre-R6 and R6 instruction encodings. Backports commit ce14bd4d469f3a14f6cbfceb6360aee066a60d72 from qemu	2018-02-17 15:24:04 -05:00
Aurelien Jarno	b5f5e2dbc2	tcg/mips: pass oi to tcg_out_tlb_load ... Instead of computing mem_index and s_bits in both tcg_out_qemu_ld and tcg_out_qemu_st function and passing them to tcg_out_tlb_load, directly pass oi to the tcg_out_tlb_load function and compute mem_index and s_bits there. Backports commit 81dfaf1a8f7f95259801da9732472f879023ef77 from qemu	2018-02-17 15:23:54 -05:00
James Hogan	dba4828444	tcg/mips: Fix clobbering of qemu_ld inputs ... The MIPS TCG backend implements qemu_ld with 64-bit targets using the v0 register (base) as a temporary to load the upper half of the QEMU TLB comparator (see line 5 below), however this happens before the input address is used (line 8 to mask off the low bits for the TLB comparison, and line 12 to add the host-guest offset). If the input address (addrl) also happens to have been placed in v0 (as in the second column below), it gets clobbered before it is used. addrl in t2 addrl in v0 1 srl a0,t2,0x7 srl a0,v0,0x7 2 andi a0,a0,0x1fe0 andi a0,a0,0x1fe0 3 addu a0,a0,s0 addu a0,a0,s0 4 lw at,9136(a0) lw at,9136(a0) set TCG_TMP0 (at) 5 lw v0,9140(a0) lw v0,9140(a0) set base (v0) 6 li t9,-4093 li t9,-4093 7 lw a0,9160(a0) lw a0,9160(a0) set addend (a0) 8 and t9,t9,t2 and t9,t9,v0 use addrl 9 bne at,t9,0x836d8c8 bne at,t9,0x836d838 use TCG_TMP0 10 nop nop 11 bne v0,t8,0x836d8c8 bne v0,a1,0x836d838 use base 12 addu v0,a0,t2 addu v0,a0,v0 use addrl, addend 13 lw t0,0(v0) lw t0,0(v0) Fix by using TCG_TMP0 (at) as the temporary instead of v0 (base), pushing the load on line 5 forward into the delay slot of the low comparison (line 10). The early load of the addend on line 7 also needs pushing even further for 64-bit targets, or it will clobber a0 before we're done with it. The output for 32-bit targets is unaffected. srl a0,v0,0x7 andi a0,a0,0x1fe0 addu a0,a0,s0 lw at,9136(a0) -lw v0,9140(a0) load high comparator li t9,-4093 -lw a0,9160(a0) load addend and t9,t9,v0 bne at,t9,0x836d838 - nop + lw at,9140(a0) load high comparator +lw a0,9160(a0) load addend -bne v0,a1,0x836d838 +bne at,a1,0x836d838 addu v0,a0,v0 lw t0,0(v0) Backports commit 33fca8589cf2aa7bf91564e6a8f26b3ba0910541 from qemu	2018-02-17 15:23:24 -05:00
Aurelien Jarno	45927edecf	tcg/mips: fix add2 ... The add2 code in the tcg_out_addsub2 function doesn't take into account the case where rl == al == bl. In that case we can't compute the carry after the addition. As it corresponds to a multiplication by 2, the carry bit is the bit 31. While this is a corner case, this prevents x86-64 guests to boot on a MIPS host. Backports commit c99d69694af4ed15b33e3f7c2e3ef6972c14358d from qemu	2018-02-17 15:23:23 -05:00
Aurelien Jarno	096d1a975d	tcg/mips: Mask TCGMemOp appropriately for indexing ... Commit 2b7ec66f fixed TCGMemOp masking following the MO_AMASK addition, but two cases were forgotten in the TCG MIPS backend. Backports commit 4214a8cb7c15ec43d4b2a43ebf248b273a0f4d45 from qemu	2018-02-17 15:23:23 -05:00
Aurelien Jarno	8396601082	tcg/mips: fix TLB loading for BE host with 32-bit guests ... For 32-bit guest, we load a 32-bit address from the TLB, so there is no need to compensate for the low or high part. This fixes 32-bit guests on big-endian hosts. Backports commit e72c4fb81db52be881c9356f1c60e0a7817d2d32 from qemu	2018-02-17 15:23:23 -05:00
Paolo Bonzini	b34c233c2f	tcg: add TCG_TARGET_TLB_DISPLACEMENT_BITS ... This will be used to size the TLB when more than 8 MMU modes are used by the target. Limitations come from the limited size of the immediate fields (which sometimes, as in the case of Aarch64, extend to instructions that shift the immediate). Backports commit 006f8638c62bca2b0caf609485f47fa5e14d8a3c from qemu	2018-02-13 08:28:29 -05:00
Richard Henderson	c5a2a50c06	tcg: Mask TCGMemOp appropriately for indexing ... The addition of MO_AMASK means that places that used inverted masks need to be changed to use positive masks, and places that failed to mask the intended bits need updating. Backports commit 2b7ec66f025263a5331f37d5ad78a625496fd7bd from qemu	2018-02-10 20:29:36 -05:00
Richard Henderson	ac713c7034	tcg: Push merged memop+mmu_idx parameter to softmmu routines ... The extra information is not yet used but it is now available. This requires minor changes through all of the tcg backends. Backports commit 3972ef6f830d65e9bacbd31257abedc055fd6dc8 from qemu	2018-02-10 20:03:22 -05:00
Richard Henderson	6234d07489	tcg: Merge memop and mmu_idx parameters to qemu_ld/st ... At the tcg opcode level, not at the tcg-op.h generator level. This requires minor changes through all of the tcg backends, but none of the cpu translators. Backports commit 59227d5d45bb3c31dc2118011691c35b3c00879c from qemu	2018-02-10 19:01:49 -05:00
Richard Henderson	00b0a50f47	tcg: Change generator-side labels to a pointer ... This is less about improved type checking than enabling a subsequent change to the representation of labels. Backports commit bec1631100323fac0900aea71043d5c4e22fc2fa from qemu	2018-02-09 14:40:59 -05:00
xorstream	1aeaf5c40d	This code should now build the x86_x64-softmmu part 2.	2017-01-19 22:50:28 +11:00
Ryan Hileman	ad5cd37551	improve multiarch support	2015-11-11 22:48:21 -08:00
Nguyen Anh Quynh	344d016104	import	2015-08-21 15:04:50 +08:00