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unicorn/qemu/target-arm
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Peter Maydell 00d06bf20e
target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL 
In v8, the illegal mode changes which are UNPREDICTABLE in v7 are
given architected behaviour:
* the mode field is unchanged
* PSTATE.IL is set (so any subsequent instructions will UNDEF)
* any other CPSR fields are written to as normal

This is pretty much the same behaviour we picked for our
UNPREDICTABLE handling, with the exception that for v8 we
need to set the IL bit.

Backports commit 81907a582901671c15be36a63b5063f88f3487e2 from qemu
2018-02-20 22:22:01 -05:00
..
arm_ldst.h import 2015-08-21 15:04:50 +08:00
cpu-qom.h target-arm: Add the pmceid0 and pmceid1 registers 2018-02-20 15:22:41 -05:00
cpu.c target-arm: Add the pmceid0 and pmceid1 registers 2018-02-20 15:22:41 -05:00
cpu.h target-arm: Add write_type argument to cpsr_write() 2018-02-20 22:15:53 -05:00
cpu64.c target-arm: Add the pmceid0 and pmceid1 registers 2018-02-20 15:22:41 -05:00
crypto_helper.c target-arm: Clean up includes 2018-02-17 21:09:32 -05:00
helper-a64.c target-arm: Move aarch64_cpu_do_interrupt() to helper.c 2018-02-18 22:23:06 -05:00
helper-a64.h import 2015-08-21 15:04:50 +08:00
helper.c target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL 2018-02-20 22:22:01 -05:00
helper.h target-arm: Give CPSR setting on 32-bit exception return its own helper 2018-02-20 22:08:35 -05:00
internals.h target-arm: Move get/set_r13_banked() to op_helper.c 2018-02-20 15:09:07 -05:00
iwmmxt_helper.c target-arm: Clean up includes 2018-02-17 21:09:32 -05:00
kvm-consts.h import 2015-08-21 15:04:50 +08:00
Makefile.objs delete sparc32_dma.h & arm-semi.c 2017-01-19 15:10:41 +08:00
neon_helper.c target-arm: Clean up includes 2018-02-17 21:09:32 -05:00
op_addsub.h import 2015-08-21 15:04:50 +08:00
op_helper.c target-arm: Raw CPSR writes should skip checks and bank switching 2018-02-20 22:17:48 -05:00
psci.c import 2015-08-21 15:04:50 +08:00
translate-a64.c target-arm: Add isread parameter to CPAccessFns 2018-02-20 11:24:17 -05:00
translate.c target-arm: Give CPSR setting on 32-bit exception return its own helper 2018-02-20 22:08:35 -05:00
translate.h tcg: Remove gen_intermediate_code_pc 2018-02-17 15:23:59 -05:00
unicorn.h arm64eb: add support for ARM64 big endian. 2017-04-24 23:30:01 +08:00
unicorn_aarch64.c target-arm: Add write_type argument to cpsr_write() 2018-02-20 22:15:53 -05:00
unicorn_arm.c target-arm: Add write_type argument to cpsr_write() 2018-02-20 22:15:53 -05:00