Peter Maydell e07cd2542c exec.c: Drop TARGET_HAS_ICE define and checks ... The TARGET_HAS_ICE #define is intended to indicate whether a target-* guest CPU implementation supports the breakpoint handling. However, all our guest CPUs have that support (the only two which do not define TARGET_HAS_ICE are unicore32 and openrisc, and in both those cases the bp support is present and the lack of the #define is just a bug). So remove the #define entirely: all new guest CPU support should include breakpoint handling as part of the basic implementation. Backports commit ec53b45bcd1f74f7a4c31331fa6d50b402cd6d26 from qemu		2018-02-18 18:17:14 -05:00
..
cpu-qom.h	remove slow cpu QOM casts (#815)	2017-05-02 14:56:39 +08:00
cpu.c	target-mips: implement the CPU wake-up on non-enabled interrupts in R6	2018-02-17 15:24:12 -05:00
cpu.h	exec.c: Drop TARGET_HAS_ICE define and checks	2018-02-18 18:17:14 -05:00
dsp_helper.c	Added MIPS support and projects for all samples.	2017-01-23 01:05:08 +11:00
helper.c	target-mips: Fix exceptions while UX=0	2018-02-17 18:57:52 -05:00
helper.h	target-mips: add PC, XNP reg numbers to RDHWR	2018-02-17 15:24:13 -05:00
lmi_helper.c	import	2015-08-21 15:04:50 +08:00
Makefile.objs	import	2015-08-21 15:04:50 +08:00
mips-defs.h	target-mips: fix MIPS64R6-generic configuration	2018-02-17 15:23:21 -05:00
msa_helper.c	target-mips: improve exception handling	2018-02-17 15:23:53 -05:00
op_helper.c	target-mips: flush QEMU TLB when disabling 64-bit addressing	2018-02-17 19:06:43 -05:00
TODO	import	2015-08-21 15:04:50 +08:00
translate.c	target-mips: add SIGRIE instruction	2018-02-17 15:24:13 -05:00
translate_init.c	target-mips: Set Config5.XNP for R6 cores	2018-02-17 15:24:13 -05:00
unicorn.c	Merge branch 'master' into msvc2	2017-04-21 01:17:00 +08:00
unicorn.h	armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition.	2017-03-15 22:25:35 +08:00