LIU Zhiwei 0f95c05ca4 target/riscv: fix vector index load/store constraints ... Although not explicitly specified that the the destination vector register groups cannot overlap the source vector register group, it is still necessary. And this constraint has been added to the v0.8 spec. Backports 3e09396e36dff4234afd6f6fd51861949be383e1		2021-03-08 12:16:45 -05:00
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arm	target/arm/cpu: Update coding style to make checkpatch.pl happy	2021-03-08 11:35:28 -05:00
i386	i386: Fix build	2021-03-05 08:35:14 -05:00
m68k	m68k: Fix build	2021-03-05 08:29:53 -05:00
mips	mips: Fix build	2021-03-05 08:51:51 -05:00
riscv	target/riscv: fix vector index load/store constraints	2021-03-08 12:16:45 -05:00
sparc	sparc: Fix build	2021-03-05 08:54:43 -05:00