Yifei Jiang 281d851303 target/riscv: raise exception to HS-mode at get_physical_address ... VS-stage translation at get_physical_address needs to translate pte address by G-stage translation. But the G-stage translation error can not be distinguished from VS-stage translation error in riscv_cpu_tlb_fill. On migration, destination needs to rebuild pte, and this G-stage translation error must be handled by HS-mode. So introduce TRANSLATE_STAGE2_FAIL so that riscv_cpu_tlb_fill could distinguish and raise it to HS-mode. Backports 33a9a57d2c31ec9ed68858911dc490b5de15f342		2021-03-08 14:43:00 -05:00
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arm	qemu/atomic.h: rename atomic_ to qatomic_	2021-03-08 14:34:35 -05:00
i386	qemu/atomic.h: rename atomic_ to qatomic_	2021-03-08 14:34:35 -05:00
m68k	m68k: Fix build	2021-03-05 08:29:53 -05:00
mips	mips: Fix build	2021-03-05 08:51:51 -05:00
riscv	target/riscv: raise exception to HS-mode at get_physical_address	2021-03-08 14:43:00 -05:00
sparc	sparc: Fix build	2021-03-05 08:54:43 -05:00